How to write ideal ADC in Hspice?

[ilter]

I have a question. How do I write ideal adc in hspice?
Can you have some examples?
Thanks.

 

[hr_rezaee]

ideal adc

hi
you can use ideal opamp and design ideal adc.

 

[ilter]

ideal adc spice

hi
you can use ideal opamp and design ideal adc.

Dear hr_rezaee,
Can you say in detail? Can you take a example?
Thanks.

 

[Humungus]

rf018.l

I don't have the HSpice manual, but I suppose HSpice has an ADC macro block ready to be used. For instance, Eldo have it.

If not, you can define your output bits by defining waves accordingly

For example, for an N-bit ADC
Dig_out=trunc(2^N*Vanalog/Vref)

B_N=trunc(Dig_out/2^(N-1))
B_N-1=trunc((Dig_out-B_N*2^(N-1))/2^(N-2))
...

Verify if TRUNC is the needed fucntion, but the idea is that.

 

[Btrend]

ideal adc hspice

I remember that,
there is a example in book, "CMOS circuit design,layout, and simulation II" by R. Jacob, Baker.

 

[ilter]

adc ideal model

I remember that,
there is a example in book, "CMOS circuit design,layout, and simulation II" by R. Jacob, Baker.

But I try , it does not run.
This is my another code.
************************************************************************
* Ideal ADC
************************************************************************
*Vin in 0 sin(2V 2V 10meg)
*vclk clk 0 pulse (0V 1.8V 0n 0.1n 0.1n 1n 2n)

*Gs1 in 1 VCR PWL(1) clk 0 0V 100M 1.8V 0.01m
*E1 2 0 1 ref1 max=1.8 min=0 le3


*vref1 ref1 0 2

.subckt ADC8bit vdd vin b7 b6 b5 b4 b3 b2 b1 b0 clock

X7 vdd vin vref0 b7 vout7 clock adcbit
X6 vdd vout7 vref1 b6 vout6 clock adcbit
X5 vdd vout6 vref2 b5 vout5 clock adcbit
X4 vdd vout5 vref3 b4 vout4 clock adcbit
X3 vdd vout4 vref4 b3 vout3 clock adcbit
X2 vdd vout3 vref5 b2 vout2 clock adcbit
X1 vdd vout2 vref6 b1 vout1 clock adcbit
X0 vdd vout1 vref7 b0 vout0 clock adcbit

v1 vref0 0 128
v2 vref1 0 64
v3 vref2 0 32
v4 vref3 0 16
v5 vref4 0 8
v6 vref5 0 4
v7 vref6 0 2
v8 vref7 0 1

.ends

.subckt adcbit vdd vin vref bitout vout clock
Gs1 vin 1 VCR clock 0 0V 100M 1.8V 0.01m
E1 bitout 0 1 vref max=1.8 min=0 1000
E2 vout 0 1 vref max=v3 min=v(1) 1000
.param v3='v(1)-vref'
.ends

X1 vdd vin b7 b6 b5 b4 b3 b2 b1 b0 clock ADC8bit
Vi vin 0 5
vclk clock 0 pulse (0V 1.8V 0n 0.1n 0.1n 1n 2n)
vd vdd 0 1.8

.option acct
.option list
.temp 25
.tran 2n 200n 1n
.op
.lib '.\rf018.l' TT
.end


But it has these error. If you know how to write adc in hspice,
please tell me detail.
Or if you can generate 12 bits digital inputs let me measure my SFDR,
please let me know how to do .
Thanks.