How to write different data to memory in different time?

[now2]

HELP

I want to write differnet data (AAA.dat, BBB.dat, CCC.dat) to memory in the different time.

In other words, the filename is a variable.

How to do it ???


What is the tpye of filename?

filename can be the module's input ?



module UU;
reg [3:0] MEM [0:9];
$readmemh(filename,MEM);
endmodule

module test;
initial begin
#1000;
filename = "AAA.dat";
#1000;
filename = "BBB.dat";
#1000;
filename = "CCC.dat";
end
endmodule

 

[gentle_man]

HELP

when will you instantate the UU module?

 

[spauls]

Re: HELP

Instead of $readmemh use $fopen your purpose will solved automatically.
BTW which compiler u are using ,

 

[now2]

Re: HELP

I use NC-verilog.


module test;

initial begin
#1000;
"I want to write AAA.dat to MEM"
#1000;
"I want to write BBB.dat to MEM"
#1000;
"I want to write CCC.dat to MEM"
end

I hope the AAA,BBB,CCC is variable.
How should I write ???


Thanks !!

 

[spauls]

Re: HELP

As i told earlier use $fopen .
please read the syntax of $fopen in Verilog 01 features , it will solve all your doubts.