how to write dc script about this?

[stormwolf]

A asic design use a pll create two clock,then there have three clock:
1. clkin ----- clock input the pll 20M
2. clkout1 ----- pll output clock1 12M
3 , clkout2 ---- pll output clock2 100M
how to write the script about the design? Or some introduce about it.
THX!!

 

[eternal_nan]

Stormwolf,

Your question is a bit vague so it is hard to answer properly. If you are
asking how to specify the clocks in your synthesis script, you would
do it like this:

create_clocks -name clkin -period 50 [get_ports <name of chip refclk input>]
create_clocks -name clkout1 -period 83.3 [get_pins <hierarchical path to PLL clkout1 output>]
create_clocks -name clkout2 -period 10 [get_pins <hierarchical path to PLL clkout2 output>]

You would probably want to set_false_path between all of these clock domains but that depends on your design.

For further help, please provide a more detailed description of your problem.

 

[sandusty]

Normally, I buffered the clock outs from PLL, and then specify clocks after those buffers. I just hard-wired the PLL but not take PLL into synthesis.