Sep 13, 2005 #1 N naveen reddy Junior Member level 3 Joined Jun 2, 2005 Messages 28 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,525 How do i write code in verilog skipping two clock cycles at a time (i.e) for every two clock cycles the output should go high pls specify weather there is any condition to get this
How do i write code in verilog skipping two clock cycles at a time (i.e) for every two clock cycles the output should go high pls specify weather there is any condition to get this
Sep 13, 2005 #2 E eda_wiz Advanced Member level 2 Joined Nov 7, 2001 Messages 653 Helped 58 Reputation 116 Reaction score 29 Trophy points 1,308 Activity points 6,195 verilog doubt you can divide you clock by 2. and then use this clock to operate the ckt.
Sep 13, 2005 #3 A amaccormack Member level 3 Joined Jul 7, 2005 Messages 58 Helped 4 Reputation 8 Reaction score 1 Trophy points 1,286 Location Scotland, UK Activity points 1,998 Re: verilog doubt Every two clock cycles the output goes high for this verilog: assign z = 1'b1; Since you never specified when it needs to go low... Seriously, though. Your English is not clear on what you want, but I guess that you either want this: always @(posedge clk or negedge nrst) if (~nrst) z <= 1'b0; else z <= ~z; which goes high every 2nd cycle or this: reg [1:0] c; assign z=c[1]; always @(posedge clk or negedge nrst) if (~nrst) c <= 2'b00; else if (c==0) c <= 2'b10; else c <= c - 2'b01; which is low for 2 cycles then high in the 3rd cycle
Re: verilog doubt Every two clock cycles the output goes high for this verilog: assign z = 1'b1; Since you never specified when it needs to go low... Seriously, though. Your English is not clear on what you want, but I guess that you either want this: always @(posedge clk or negedge nrst) if (~nrst) z <= 1'b0; else z <= ~z; which goes high every 2nd cycle or this: reg [1:0] c; assign z=c[1]; always @(posedge clk or negedge nrst) if (~nrst) c <= 2'b00; else if (c==0) c <= 2'b10; else c <= c - 2'b01; which is low for 2 cycles then high in the 3rd cycle
Sep 13, 2005 #4 N nand_gates Advanced Member level 3 Joined Jul 19, 2004 Messages 899 Helped 175 Reputation 350 Reaction score 53 Trophy points 1,308 Activity points 7,037 Re: verilog doubt This is what you are looking for............. Hope this helps! Code: module div3 (clk, reset_n, out); input clk, reset_n; output out; reg [2:0] count; assign out = count[1]; always @(posedge clk or negedge reset_n) if (!reset_n) count <= 0; else if (count == 2'b10) count <= 0; else count <= count + 1; endmodule // div3
Re: verilog doubt This is what you are looking for............. Hope this helps! Code: module div3 (clk, reset_n, out); input clk, reset_n; output out; reg [2:0] count; assign out = count[1]; always @(posedge clk or negedge reset_n) if (!reset_n) count <= 0; else if (count == 2'b10) count <= 0; else count <= count + 1; endmodule // div3
Sep 13, 2005 #5 A anjali Full Member level 3 Joined Aug 16, 2005 Messages 173 Helped 14 Reputation 28 Reaction score 6 Trophy points 1,298 Activity points 3,033 Re: verilog doubt you want to generate a signal whivh goes high for every 2 clock cycles. i think this code will gives you that. module ex(clk,reset,out); input clk,reset; output clk; reg flag; assign out = flag; always @(posedge clk or negedge reset) begin if(!reset) flag <= 0; else flag <= ~flag; end endmodule
Re: verilog doubt you want to generate a signal whivh goes high for every 2 clock cycles. i think this code will gives you that. module ex(clk,reset,out); input clk,reset; output clk; reg flag; assign out = flag; always @(posedge clk or negedge reset) begin if(!reset) flag <= 0; else flag <= ~flag; end endmodule