Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi,i observed this option of changing to analog,but my doubt is how to get sinusoid in vhdl or verilog,from there only i can simulate it and view,any how thanq for ur help plz respond.
Both Verilog and VHDL provide math functions such as sin(), cos(), sqrt(), etc.
They are very helpful in simulation, but remember synthesis tools usually don't support them.
Do you mean the DCM in a Xilinx FPGA? It has a synthesizer for generating square wave clocks at various frequencies, but it won't be very useful for making sinewaves.
A DDS (Direct Digital Synthesizer) is one easy way to make very good numerical sinewaves. Check your software documentation, you may already have a DDS library component or core. For example, Xilinx ISE 9.1i Core Generator includes "DDS Compiler 2.0" and "Direct Digital Synthesizer 5.0".
In the Modelsim waveform window, select the signal in question, right click and select Format.. -> Analog... and then configure it to display the way you'd like to see it..
after changing it to analog in wave properties am not able to get the sine wave , is it a matter concerned with the version of modelsim ?? this question arises becoz am trying to generate a sine wave for my project
---------- Post added at 17:52 ---------- Previous post was at 17:47 ----------
as a new bee into vhdl i have a question what are those
1.analog step
2.analog interpolated
3.analog backstep
in wave properties after changing it to analog ??
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
