Hi...
How do i reduce the threshold voltage(Vth) of a single NMOS transistor in a circuit?the model file specifies 0.37v(TSMC 90nm node) but for my circuit i need the Vth to be around 0.2v,applying body bias increases the threshold voltage,how to reduce the Vth??
It is very possible that in your spec. you have NMOS with adjusted threshold voltage already and if it so you can ask fabs if they could change adjusted dopping concentration for NMOS (I am not sure they will agree to change zero-threshold voltage ).
In practice the zero-threshold voltage may not be suited to circuit design and is typically adjusted by implantation of dopands into the channel during device fabrication in order to obtain enchantment device.
Basic idea of varying threshold voltage is altering the doping level of the substrate near the oxide interface.
IMHO if you have just only one device with Vth0=0.2V and all another have Vth0 = 0.37V no one will produce such device ( in this case you have to modify your circuit. E.g. body effect can be eliminate by using PMOS device )