zongya
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Hi all,
I'm trying to simulate a current-controlled current source written in veriloga. Here is the code:
However, for the control current pc and nc, how could I properly connect them to the cccs verilog symbol? I know for normal Cadence cccs we have a "vref" for the control current. But I tried to create the same vref and connect the two "+ -" wires of vref to pc and nc and it shows me error.
Could anyone help me with it? Thanks in advance!
I'm trying to simulate a current-controlled current source written in veriloga. Here is the code:
Code:
// current-controlled current source
// current-controlled current source
module cccs(p,n,pc,nc);
inout p,n;
input pc,nc;
electrical p,n,pc,nc;
parameter real gain=0;
analog
I(p,n) <+ gain*I(pc,nc);
endmodule;However, for the control current pc and nc, how could I properly connect them to the cccs verilog symbol? I know for normal Cadence cccs we have a "vref" for the control current. But I tried to create the same vref and connect the two "+ -" wires of vref to pc and nc and it shows me error.
Could anyone help me with it? Thanks in advance!