How to use VCS to watch the internal memory in my design?

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vcdplusmemon

I have defined two memory in my design:

reg [15:0] dmem [31:0];
reg [15:0] imem[31:0];

I hope to watch the value in these memory when using VCS debugging.

But I can not find these memory from the item list.
 

memory dumping in vcs

when you dump, add the "aggregate" option
 

$vcdplusmemon

Checkout this!
-------------------------------------------------------------
vcs -PP +memcbk Testbench.v -R
vcs -RPP +vpdfile+vcdplus.vpd
-------------------------------------------------------------
Code: 
`timescale 1ns/100ps

module Testbench;

  integer i;
  reg       R1[7:0];
  reg [3:0] R2[7:0];

  initial  begin
	for (i=0; i<8; i=i+1) begin
	  R1[i] = 1'b0;
	  R2[i] = 4'h0;
	end

	#10;

	for (i=0; i<8; i=i+1) begin
	  R1[i] = 1'b1;
	  R2[i] = 4'hf;
	end
  end


  initial begin
	$vcdpluson();
	$vcdplusmemon();
  end
endmodule
 

vcs dump memory contents

what version of vcs u r using?
vcs comes in 2 gui, virsim and dve.

if you are using dve, there wont b any problem. follow the steps below:
1. vcs -debug <your filename>
2. simv -gui
it will bring up dve. at first glance you cannt c your mem
use ur mouse right click on the signal in hierarchy panel (the left most one), choose "add dump", in the dialog, check Aggregate.

you have to re-simulate your design under dve - Simulator -> Rebuid & start, then you will c ur memory instance now!

BTW, anyone know how to display using Virsim? I only know how to do it in dve.
 

memcbk

I jst figure it out lately.
if you want to display the memory content using virsim, here is what u can do:


in the interactive window, key in the following command in the command text box:
$vcdplusmemon

and that's it! you can c the mem in the signal panel, inside the hierarchy browser
 

vcs memcbk

use latest verdi from Novas company, they can infer the memory content based on read/write history. very cute.
 

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