ijalab
Junior Member level 1
We have a Reference Clock and that should go to the chip only when calibration is required.
I have a CLK_signal line which when goes
High indicates the need for reference clock for calibration
Low indicating ref clock not needed
And this clock signal line should transfer the clock to the chip after a programmable delay of say 5ms if high.
so, this is just an AND gate with a delay, where AND gate's inputs are clk_signal and the clock itself.
How do I use R&S SML 03 for this purpose?
thanks,
I have a CLK_signal line which when goes
High indicates the need for reference clock for calibration
Low indicating ref clock not needed
And this clock signal line should transfer the clock to the chip after a programmable delay of say 5ms if high.
so, this is just an AND gate with a delay, where AND gate's inputs are clk_signal and the clock itself.
How do I use R&S SML 03 for this purpose?
thanks,