[SOLVED] How to use Oscillator clock in Xilinx V6 ml605 board

[syedshan]

Hello every one
This is shan

I have to design a system where I have to use the Oscillator clock of the ML605 virtex 6 board. This clock is differential clock with fpga ports H9,J9...

I need guidance in this regard. I describe the system clock for my design in verilog as :

input clk; //this is now the single port for clock input

But in board oscillator there are differential output to clock so how should I attach the clock to my designed system. Is there any way of making this differential clock single ended. awaiting you reply.

i have searched for good time and could not find proper solution to that.


Regards,
Shan

 

[joelby]

Sure, just use an IBUFGDS component to convert your external differential clock into a single ended, globally buffered low skew clock. Have a hunt through the language templates to find it.

 

[syedshan]

Thank you dear,

Well during trying I got to know about DCM.
can this thing work for me. Any ways I will try both things... Do tell me about DCM if you know...
Thanks any ways

Regards,
Shan

 

[ravics]

You need not use the differential clock. There is a socket crystal oscillator of 66.667 MHz available on board. Check UCF pin "U23".

 

[syedshan]

Thank you for your response...

Yes it is one way for my project my supervisor need me to use the oscillator clock since its gives 200MHz while the other gives around 66MHz.
Is there any way to sort out

Well Thank you for your reply

Regards,
Shan

 

[ravics]

I didn't understand your problem. You may use the user clock (66.67 MHz) & use custom logic/ DCM to derive another clock if required.

 

[syedshan]

just connect the positive port J9 and the negative pair will automatically be connected

Shan

 

[joelby]

That's a bit misleading. If it's a single-ended clock source, just connect it to the positive input (or negative, it doesn't matter because they're the same). The other output isn't automatically connected to anything - it's spare and can be used for something else. If it's a differential clock source, you have to connect both inputs to the source.

On the FPGA, instantiate either a single-ended or differential input buffer as appropriate.

 

[syedshan]

Yes practically inside FPGA, yes you are right it is this way...
But I am only talking about Plan-Ahead pin connection for your ucf file...

I tried this way. It only showed one port (positive differential pin) so to me this is the solution...
Any way I would really like to know more if you think I have missed something because of which this happens....
I also tried to connect H9 to that same port (in Plan ahead ) but it prompted error straight away stating that a positive pin should be connected...

Waiting for your response

Bests
Shan

 

[joelby]

Are you using a differential clock source? What sort of input buffer are you using - IBUFG or IBUFGDS? Or are you not instantiating a buffer?

 

[syedshan]

yes I am using differential clock source of 200Mhz inside the ml605 board.

I am using BUFG ( though I do not have the clearest of idea about buffer, but the more I use it , the more clearer it gets...)

Well please check the following code and ucf I made and downloaded in fpga as well ..

# PlanAhead Generated physical constraints 

NET "CLK_IN1_P" LOC = J9;
NET "cnt[24]" LOC = AC22;
NET "rst" LOC = D22;

module cnet(
    input CLK_IN1_P,CLK_IN1_N,
    input rst,
    output reg [24:0] cnt    );

always@(posedge CLK_OUT1)
if(rst)
	cnt <= 25'd0;
	else cnt <= cnt + 1'b1;

//Clock Instantiation
  clk1 pc1
   (// Clock in ports
    .CLK_IN1_P(CLK_IN1_P),    // IN
    .CLK_IN1_N(CLK_IN1_N),    // IN
    .CLK_OUT1(CLK_OUT1));    // OUT

endmodule

Please do reply. It will be more learning

Many thanks and Best regards,
Shan

 

[joelby]

When you created the clocking core using the Clocking Generator Wizard, what did you specify as the source for your primary input clock? It should be "Differential clock capable pin".

Other than that I can't see anything wrong with your code other than the missing CLK_IN1_N definition in the UCF (if you leave it out, the tools will pick one for you, which you don't want).

 

[syedshan]

Yes it was differential clock of 200 mhz crystal embedded on the ml605 board. So in response wizard generated the single pin clock of 100 MhZ output.

(please if you can confirm one thing it will be great). When in clocking wizard I select input clock to be 200 mhz clock I selected BUFG (does it means that my clock will be distributed thru out the FPGA using global lcok buffer), what if I had directly selected BUGH or any other buffer by passing BUFG

 

[joelby]

For information on the difference between BUFG and BUFH, please read UG362.

"The horizontal clock buffer (BUFH) drives a horizontal global clock tree spine in a single region (Figure 1-27). Each region has 12 BUFHs available."

Also, I retract what I said about using the negative pin with a single-ended clock - there are some caveats on the Virtex:

"There are 32 global clock buffers in every Virtex-6 device. A global clock input can directly connect from the P-side of the differential input pin pair to any global clock buffer input. There are eight global clock pin inputs. The top/bottom half rules from previous Virtex architectures no longer apply. Each differential global clock pin pair can connect to either a differential or single-ended clock on the PCB. If using a single-ended clock, then the P-side of the pin pair must be used because a direct connection only exists on this pin. For pin naming conventions please refer to the Virtex-6 FPGA Packaging and Pinout Specification. If a single-ended clock is connected to the P-side of a differential pin pair, then the N-side can not be used as another single-ended clock pin. However, it can be used as a user I/O."

 

[syedshan]

Great thanks...