How to use MOS capacitance in a design?

[smpai]

Has anyone used MOS capacitance in any of the design? AS the literature says, there is some non-linearization in the C-V characterisation. Any comments to improvise>?

 

[Fractional-N]

how to use mos for constant capacitance

do you mean to use a MOS transistor as a capacitor?
if yes. it is simple, just tie drain and source together and body to GND or VDD for nmos or pmos. then you'll have a capacitor between gate and drain-source (tied together). take care in this configuration source and drain voltages should not go below GND or above VDD. you can also connect the body to drain and source instead of supply rails. each of these configurations have different C-V characteristics.
it is easy to simulate these mos-caps in hspice and see the characteristic

 

[smpai]

pmos capacitance pdf

Thanks for the reply...I have tried characterising both the configurations...I need to use the case with back-gate connected to gnd for nmos...In this case do we have any compensation techniques to eradicate non-linearity in CV chs.?? I have found many such techniques for the configuration where bulk or the back-gate is taken as terminal..

 

[coolstuff07]

hspice cv chracteristics

Hi,

How to simulate in Hspice to see C-V charcteristics.

Bye.

 

[Fractional-N]

simple mos capacitance model

Hi,

How to simulate in Hspice to see C-V charcteristics.

Bye.

hi,
here is a file i use to see C-V charac. ask questions if you can't understand the netlist.

 

[Fractional-N]

nmos capacitance model

Thanks for the reply...I have tried characterising both the configurations...I need to use the case with back-gate connected to gnd for nmos...In this case do we have any compensation techniques to eradicate non-linearity in CV chs.?? I have found many such techniques for the configuration where bulk or the back-gate is taken as terminal..

oh! sorry i don't have any information about compensating the varactor non-linearity. by the way there is regions in C-V charac of a varactor that capacitance value is constant (not changing with voltage) you can use those regions by applying the appropriate voltage across the MOS varactor.
regards.

 

[Sadegh.j]

cv-mos

I think the BEST tutorial to teach you about CMOS caps is here:

**broken link removed**

You simulate the transistors your self and see the output form. I strongly recommend it.

Also, The solid state book by Streetman gives you a physical interpretation of these Caps, if you are interested.

to use them, you have to restrict your swing to the linear region of the caps.

Cheers