How to use IP cores in Xilinx ?

[sandeep_sggs]

hi m a biginner in verilog/vhdl. i want to know about How to use IP cores?? Also if they(ip cores ) are fully freely available. I Am using Xilinx9.1i Kindly help me.
some specific literature is always welcom.
thanks and regards

 

[asicganesh]

Re: Xilinx IP cores

Try to use Xilinx Core Generator to generate a IP core (Netlist in EDIF or NGC Format)

It will give u the entity or top module port details after you select suitable parameters for the core.

u can then port map or instantiate this core from your design..

 

[cheggy]

Re: Xilinx IP cores

Hi,

There are many free cores included in your ISE, you may check `em out by using Core Generator. Just "add new source" in your project and choose Core Generator file to be added, then you'll see the list of available cores. When once created, core's .xco file may be included in your design.

 

[shiv_emf]

Xilinx IP cores

Well when u have ISE then u can explore many things. U can do full flow ASIC design.

To start with ! u can just try implementing divider circuit.