How to use interrupt with local ip interrupt controller

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spk_lionking

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Hi everybody,

I have some problem about low-latency interrupt mode in MicroBlaze.

If i don't use XPS_INTC of Xilinx, I use my interrupt controller. So, I have to prepare what function or lib to implement fast interrupt handle in my project. Example, i see some funtion in XPS_INTC of Xilinx such as XIntc_Connect, XIntc_ConnectFastHandle,... or something likes that, so may I also need corresponding fuction/lib with my interrupt controller like that, right ???

My IP use APB interface, so I add "AXI to APB bridge" to my SoPC. It causes no address map, ID... for my IP, so I use base address of "AXI to APB bridge" instead. It works when I want to write/read data to register in my IP interrupt controller.

The most important thing right now, how I implement interrupt hander with my interrupt controller. I really need your help to resolve this embarrassing.

Hope yours reply soon,

Best Regards,

Tuan Nguyen



Regards,

Tuan Nguyen
 




sure you need to write low level driver.
why don't you use the axi intc ? it has fast interupt mode.
 

aruipksni said:
sure you need to write low level driver.
why don't you use the axi intc ? it has fast interupt mode.
Click to expand...

thank you for reply me. Because that is my exercise, "implementation interrupt controller". I wanna add my interrupt controller to the SoPC and write some application interrupt handle. But i have no idea how to write low level driver just you say, my IP support low-latency interrupt mode( use 3 signal interrupt, interrupt address and interrupt_ack from MicroBlaze ), any suggestion about low driver for me ???
 


my basic thought is to copy existing intc driver and just modify the
xintc_l.h to adjust it to your needs with your registers/addresses ext....

you can read more in :
https://www.xilinx.com/support/documentation/application_notes/xapp778.pdf
 
aruipksni said:
my basic thought is to copy existing intc driver and just modify the
xintc_l.h to adjust it to your needs with your registers/addresses ext....

you can read more in :
https://www.xilinx.com/support/documentation/application_notes/xapp778.pdf
Click to expand...

Thanks about this information.

I am writing low driver for my interrupt controller. I have trouble at here, I create function which connect between ID of interrupt and corresponding interrupt handle for each individual interrupt like that:
Code: 
MyIntc_Connect(MyIntc * InstancePtr, u8 Id,
		  XInterruptHandler Handler, void *CallBackRef)

I have problem with second parameter, I don't see declare parameter about ID number of interrupt sources in xparameter.h, so how MyIntc_Connect work if no ID, can I insert them to xparameter.h ???
 

it's been some time since i mess with edk.
i think you need to add to int in your costom ip mpd file :

PORT Interrupt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING, INTERRUPT_PRIORITY = LOW
 

aruipksni said:
it's been some time since i mess with edk.
i think you need to add to int in your costom ip mpd file :

PORT Interrupt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING, INTERRUPT_PRIORITY = LOW
Click to expand...

I don't sure PORT Interrupt just you write above, its a interrupt input source or output to MicroBlaze ???
This is mpd file of my interrupt controller:
Code: 
BEGIN intc

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = USER


## Bus Interfaces
BUS_INTERFACE BUS = INTERRUPT, BUS_STD = XIL_MBINTERRUPT, BUS_TYPE = INITIATOR
## Generics for VHDL or Parameters for Verilog

## Ports
PORT req_int = Interrupt, DIR = O, SIGIS = INTERRUPT, BUS = INTERRUPT, PERMIT = BASE_USER, DESC = 'Interrupt Request Output'
PORT vect_int = Interrupt_Address, DIR = O, VEC = [31:0], VEC = [31:0], ENDIAN = LITTLE, BUS = INTERRUPT, PERMIT = BASE_USER, DESC = 'Interrupt Vector Address Output'
PORT i = Interrupt_Ack, DIR = I, VEC = [1:0], ENDIAN = LITTLE, BUS = INTERRUPT, PERMIT = BASE_USER, DESC = 'Interrupt Acknowledgement Input'
PORT prdata = "", DIR = O, VEC = [31:0]
PORT pslverr = "", DIR = O
PORT pclk = "", DIR = I
PORT preset = "", DIR = I
PORT pwrite = "", DIR = I
PORT psel = "", DIR = I
PORT penable = "", DIR = I
PORT paddr = "", DIR = I, VEC = [31:0]
PORT pwdata = "", DIR = I, VEC = [31:0]
PORT ext_event = "", DIR = I, VEC = [7:0]
PORT nmi_event = "", DIR = I
PORT irq_in = "", DIR = I, VEC = [3:0]

END

ext_event, external interrupt sources, I am going to connect it to 8 switch
nmi_event, internal interrupt request from AXI timer
irq_in, interrupt request demo from 4 putton

How I can make the ID number for each interrupt ???
 

input ports should also have interupt attributes.

PORT Intr = "", DIR = I, VEC = [(C_NUM_INTR_INPUTS-1):0], SIGIS = INTERRUPT, ENDIAN = LITTLE, PERMIT = BASE_USER, DESC = 'Interrupt Inputs'

ID are based uppon your interupt connection order to intc.
 
aruipksni said:
input ports should also have interupt attributes.

PORT Intr = "", DIR = I, VEC = [(C_NUM_INTR_INPUTS-1):0], SIGIS = INTERRUPT, ENDIAN = LITTLE, PERMIT = BASE_USER, DESC = 'Interrupt Inputs'

ID are based uppon your interupt connection order to intc.
Click to expand...

If I insert the line just like you write above, it mean have a priority for each interrupt source[L to H], right ??? But I don't want this priority because my interrupt controller support "programmable priority" for each interrupt already, you have a way what to ignore this ?? because i just only configure priority inside my interrrupt controller throughout registers
 


the priority is established in the intc - ID numbers are basiclly numbers.
my main point was that you must give interupt attributes so edk will give you the parameters in the MHS.
 

aruipksni said:
the priority is established in the intc - ID numbers are basiclly numbers.
my main point was that you must give interupt attributes so edk will give you the parameters in the MHS.
Click to expand...

I do it just like you say but in xparameter.h still not ID for interrupt source

Code: 
## Ports
PORT req_int = Interrupt, DIR = O, SIGIS = INTERRUPT, BUS = INTERRUPT, PERMIT = BASE_USER, DESC = 'Interrupt Request Output'
PORT vect_int = Interrupt_Address, DIR = O, VEC = [31:0], VEC = [31:0], ENDIAN = LITTLE, BUS = INTERRUPT, PERMIT = BASE_USER, DESC = 'Interrupt Vector Address Output'
PORT i = Interrupt_Ack, DIR = I, VEC = [1:0], ENDIAN = LITTLE, BUS = INTERRUPT, PERMIT = BASE_USER, DESC = 'Interrupt Acknowledgement Input'
PORT prdata = "", DIR = O, VEC = [31:0]
PORT pslverr = "", DIR = O
PORT pclk = "", DIR = I
PORT preset = "", DIR = I
PORT pwrite = "", DIR = I
PORT psel = "", DIR = I
PORT penable = "", DIR = I
PORT paddr = "", DIR = I, VEC = [31:0]
PORT pwdata = "", DIR = I, VEC = [31:0]
#PORT ext_event = "", DIR = I, VEC = [7:0]
#PORT nmi_event = "", DIR = I
#PORT irq_in = "", DIR = I, VEC = [3:0]
PORT ext_event =  "", DIR = I, VEC = [7:0], SIGIS = INTERRUPT, ENDIAN = LITTLE, PERMIT = BASE_USER, DESC = 'Interrupt Inputs'
PORT nmi_event =  "", DIR = I, SIGIS = INTERRUPT, ENDIAN = LITTLE, PERMIT = BASE_USER, DESC = 'Interrupt Inputs'
PORT irq_in =  "", DIR = I, VEC = [3:0], SIGIS = INTERRUPT, ENDIAN = LITTLE, PERMIT = BASE_USER, DESC = 'Interrupt Inputs'
 


Did you connect all interupt sources ?
 

aruipksni said:
Did you connect all interupt sources ?
Click to expand...

indeed. I conntect to all interrupt source "ext_event" ,"nmi_event" and "irq_in". any problem about this ??? Besides, I edit it in mpid file right??
But still no ID interrupt na. You can see my xparameter.h below
Attachment:

Code: 
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.6 EDK_P.68d
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

* 
* Description: Driver parameters
*
*******************************************************************/

#define STDIN_BASEADDRESS 0x41400000
#define STDOUT_BASEADDRESS 0x41400000

/******************************************************************/


/* Definitions for peripheral AXI_APB_BRIDGE_0 */
#define XPAR_AXI_APB_BRIDGE_0_BASEADDR 0x79400000
#define XPAR_AXI_APB_BRIDGE_0_HIGHADDR 0x7940FFFF


/* Definitions for peripheral DIGILENT_SEVSEG_DISP */
#define XPAR_DIGILENT_SEVSEG_DISP_BASEADDR 0x7D600000
#define XPAR_DIGILENT_SEVSEG_DISP_HIGHADDR 0x7D60FFFF


/* Definitions for peripheral DIGILENT_SHARED_MEM_BUS_MUX */
#define XPAR_DIGILENT_SHARED_MEM_BUS_MUX_QSPI_BASEADDR 0x72800000
#define XPAR_DIGILENT_SHARED_MEM_BUS_MUX_QSPI_HIGHADDR 0x7280FFFF
#define XPAR_DIGILENT_SHARED_MEM_BUS_MUX_PSRAM_BASEADDR 0x43000000
#define XPAR_DIGILENT_SHARED_MEM_BUS_MUX_PSRAM_HIGHADDR 0x43FFFFFF
#define XPAR_DIGILENT_SHARED_MEM_BUS_MUX_FLASH_BASEADDR 0x42000000
#define XPAR_DIGILENT_SHARED_MEM_BUS_MUX_FLASH_HIGHADDR 0x42FFFFFF


/******************************************************************/

/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1

/* Definitions for peripheral AXI_TIMER_0 */
#define XPAR_AXI_TIMER_0_DEVICE_ID 0
#define XPAR_AXI_TIMER_0_BASEADDR 0x41C00000
#define XPAR_AXI_TIMER_0_HIGHADDR 0x41C0FFFF
#define XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ 100000000


/******************************************************************/

/* Canonical definitions for peripheral AXI_TIMER_0 */
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_AXI_TIMER_0_DEVICE_ID
#define XPAR_TMRCTR_0_BASEADDR 0x41C00000
#define XPAR_TMRCTR_0_HIGHADDR 0x41C0FFFF
#define XPAR_TMRCTR_0_CLOCK_FREQ_HZ XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ

/******************************************************************/

/* Definitions for driver UARTLITE */
#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral DEBUG_MODULE */
#define XPAR_DEBUG_MODULE_BASEADDR 0x41400000
#define XPAR_DEBUG_MODULE_HIGHADDR 0x4140FFFF
#define XPAR_DEBUG_MODULE_DEVICE_ID 0
#define XPAR_DEBUG_MODULE_BAUDRATE 0
#define XPAR_DEBUG_MODULE_USE_PARITY 0
#define XPAR_DEBUG_MODULE_ODD_PARITY 0
#define XPAR_DEBUG_MODULE_DATA_BITS 0


/******************************************************************/

/* Canonical definitions for peripheral DEBUG_MODULE */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_DEBUG_MODULE_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0x41400000
#define XPAR_UARTLITE_0_HIGHADDR 0x4140FFFF
#define XPAR_UARTLITE_0_BAUDRATE 0
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 0
#define XPAR_UARTLITE_0_SIO_CHAN -1


/******************************************************************/

/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1

/* Definitions for peripheral LEDS_8BITS */
#define XPAR_LEDS_8BITS_BASEADDR 0x40000000
#define XPAR_LEDS_8BITS_HIGHADDR 0x4000FFFF
#define XPAR_LEDS_8BITS_DEVICE_ID 0
#define XPAR_LEDS_8BITS_INTERRUPT_PRESENT 0
#define XPAR_LEDS_8BITS_IS_DUAL 0


/******************************************************************/

/* Canonical definitions for peripheral LEDS_8BITS */
#define XPAR_GPIO_0_BASEADDR 0x40000000
#define XPAR_GPIO_0_HIGHADDR 0x4000FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_LEDS_8BITS_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_GPIO_0_IS_DUAL 0


/******************************************************************/

/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 2

/* Definitions for peripheral MICROBLAZE_0_D_BRAM_CTRL */
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_DEVICE_ID 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_FAULT_INJECT 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_CE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_UE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC_STATUS_REGISTERS 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_CE_COUNTER_WIDTH 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC_ONOFF_REGISTER 0
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 1
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_WRITE_ACCESS 2
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_HIGHADDR 0x00003FFF
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFF 
#define XPAR_MICROBLAZE_0_D_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF 


/* Definitions for peripheral MICROBLAZE_0_I_BRAM_CTRL */
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_DEVICE_ID 1
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC 0
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_FAULT_INJECT 0
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_CE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_UE_FAILING_REGISTERS 0
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC_STATUS_REGISTERS 0
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_CE_COUNTER_WIDTH 0
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC_ONOFF_REGISTER 0
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC_ONOFF_RESET_VALUE 1
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_WRITE_ACCESS 2
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_HIGHADDR 0x00003FFF
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_S_AXI_CTRL_BASEADDR 0xFFFFFFFF 
#define XPAR_MICROBLAZE_0_I_BRAM_CTRL_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF 


/******************************************************************/

/* Canonical definitions for peripheral MICROBLAZE_0_D_BRAM_CTRL */
#define XPAR_BRAM_0_DEVICE_ID XPAR_MICROBLAZE_0_D_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_0_WRITE_ACCESS 2
#define XPAR_BRAM_0_BASEADDR 0x00000000
#define XPAR_BRAM_0_HIGHADDR 0x00003FFF

/* Canonical definitions for peripheral MICROBLAZE_0_I_BRAM_CTRL */
#define XPAR_BRAM_1_DEVICE_ID XPAR_MICROBLAZE_0_I_BRAM_CTRL_DEVICE_ID
#define XPAR_BRAM_1_DATA_WIDTH 32
#define XPAR_BRAM_1_ECC 0
#define XPAR_BRAM_1_FAULT_INJECT 0
#define XPAR_BRAM_1_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_1_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_1_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_1_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_1_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_1_ECC_ONOFF_RESET_VALUE 1
#define XPAR_BRAM_1_WRITE_ACCESS 2
#define XPAR_BRAM_1_BASEADDR 0x00000000
#define XPAR_BRAM_1_HIGHADDR 0x00003FFF


/******************************************************************/

/* Definitions for bus frequencies */
#define XPAR_CPU_M_AXI_DP_FREQ_HZ 100000000
#define XPAR_CPU_M_AXI_IP_FREQ_HZ 100000000
/******************************************************************/

/* Canonical definitions for bus frequencies */
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
/******************************************************************/

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000
#define XPAR_MICROBLAZE_CORE_CLOCK_FREQ_HZ 100000000

/******************************************************************/


/* Definitions for peripheral MICROBLAZE_0 */
#define XPAR_MICROBLAZE_0_SCO 0
#define XPAR_MICROBLAZE_0_FREQ 100000000
#define XPAR_MICROBLAZE_0_DATA_SIZE 32
#define XPAR_MICROBLAZE_0_DYNAMIC_BUS_SIZING 1
#define XPAR_MICROBLAZE_0_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_0_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_0_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_0_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_0_ENDIANNESS 1
#define XPAR_MICROBLAZE_0_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_0_OPTIMIZATION 0
#define XPAR_MICROBLAZE_0_INTERCONNECT 2
#define XPAR_MICROBLAZE_0_STREAM_INTERCONNECT 0
#define XPAR_MICROBLAZE_0_BASE_VECTORS 0x00000000
#define XPAR_MICROBLAZE_0_DPLB_DWIDTH 32
#define XPAR_MICROBLAZE_0_DPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_0_DPLB_BURST_EN 0
#define XPAR_MICROBLAZE_0_DPLB_P2P 0
#define XPAR_MICROBLAZE_0_IPLB_DWIDTH 32
#define XPAR_MICROBLAZE_0_IPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_0_IPLB_BURST_EN 0
#define XPAR_MICROBLAZE_0_IPLB_P2P 0
#define XPAR_MICROBLAZE_0_M_AXI_DP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_0_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_0_M_AXI_DP_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_0_M_AXI_DP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_0_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_0_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_0_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
#define XPAR_MICROBLAZE_0_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
#define XPAR_MICROBLAZE_0_M_AXI_IP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_0_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_0_M_AXI_IP_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_0_M_AXI_IP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_0_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_0_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
#define XPAR_MICROBLAZE_0_D_AXI 1
#define XPAR_MICROBLAZE_0_D_PLB 0
#define XPAR_MICROBLAZE_0_D_LMB 1
#define XPAR_MICROBLAZE_0_I_AXI 1
#define XPAR_MICROBLAZE_0_I_PLB 0
#define XPAR_MICROBLAZE_0_I_LMB 1
#define XPAR_MICROBLAZE_0_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_0_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_0_USE_BARREL 1
#define XPAR_MICROBLAZE_0_USE_DIV 0
#define XPAR_MICROBLAZE_0_USE_HW_MUL 1
#define XPAR_MICROBLAZE_0_USE_FPU 0
#define XPAR_MICROBLAZE_0_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS 0
#define XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION 0
#define XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION 0
#define XPAR_MICROBLAZE_0_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_0_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_0_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_0_PVR 0
#define XPAR_MICROBLAZE_0_PVR_USER1 0x00
#define XPAR_MICROBLAZE_0_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_0_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_0_NUMBER_OF_PC_BRK 1
#define XPAR_MICROBLAZE_0_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_0_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_0_INTERRUPT_IS_EDGE 1
#define XPAR_MICROBLAZE_0_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_0_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_0_OPCODE_0X0_ILLEGAL 0
#define XPAR_MICROBLAZE_0_FSL_LINKS 0
#define XPAR_MICROBLAZE_0_FSL_DATA_SIZE 32
#define XPAR_MICROBLAZE_0_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_0_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_0_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_ICACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_ICACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_0_USE_ICACHE 0
#define XPAR_MICROBLAZE_0_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_0_ADDR_TAG_BITS 0
#define XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_0_ICACHE_USE_FSL 0
#define XPAR_MICROBLAZE_0_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_0_ICACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_0_ICACHE_INTERFACE 0
#define XPAR_MICROBLAZE_0_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_0_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_0_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_0_M_AXI_IC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_0_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_0_M_AXI_IC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_0_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_IC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_0_M_AXI_IC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_0_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
#define XPAR_MICROBLAZE_0_DCACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_0_DCACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_0_USE_DCACHE 0
#define XPAR_MICROBLAZE_0_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_0_DCACHE_ADDR_TAG 0
#define XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_0_DCACHE_USE_FSL 0
#define XPAR_MICROBLAZE_0_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_0_DCACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_0_DCACHE_INTERFACE 0
#define XPAR_MICROBLAZE_0_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_0_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_0_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_0_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_0_M_AXI_DC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_0_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_0_M_AXI_DC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_0_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_0_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_0_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
#define XPAR_MICROBLAZE_0_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
#define XPAR_MICROBLAZE_0_USE_MMU 0
#define XPAR_MICROBLAZE_0_MMU_DTLB_SIZE 4
#define XPAR_MICROBLAZE_0_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_0_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_0_MMU_ZONES 16
#define XPAR_MICROBLAZE_0_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_0_USE_INTERRUPT 2
#define XPAR_MICROBLAZE_0_USE_EXT_BRK 1
#define XPAR_MICROBLAZE_0_USE_EXT_NM_BRK 1
#define XPAR_MICROBLAZE_0_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_0_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_0_PC_WIDTH 32

/******************************************************************/

#define XPAR_CPU_ID 0
#define XPAR_MICROBLAZE_ID 0
#define XPAR_MICROBLAZE_SCO 0
#define XPAR_MICROBLAZE_FREQ 100000000
#define XPAR_MICROBLAZE_DATA_SIZE 32
#define XPAR_MICROBLAZE_DYNAMIC_BUS_SIZING 1
#define XPAR_MICROBLAZE_AVOID_PRIMITIVES 0
#define XPAR_MICROBLAZE_FAULT_TOLERANT 0
#define XPAR_MICROBLAZE_ECC_USE_CE_EXCEPTION 0
#define XPAR_MICROBLAZE_LOCKSTEP_SLAVE 0
#define XPAR_MICROBLAZE_ENDIANNESS 1
#define XPAR_MICROBLAZE_AREA_OPTIMIZED 0
#define XPAR_MICROBLAZE_OPTIMIZATION 0
#define XPAR_MICROBLAZE_INTERCONNECT 2
#define XPAR_MICROBLAZE_STREAM_INTERCONNECT 0
#define XPAR_MICROBLAZE_BASE_VECTORS 0x00000000
#define XPAR_MICROBLAZE_DPLB_DWIDTH 32
#define XPAR_MICROBLAZE_DPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_DPLB_BURST_EN 0
#define XPAR_MICROBLAZE_DPLB_P2P 0
#define XPAR_MICROBLAZE_IPLB_DWIDTH 32
#define XPAR_MICROBLAZE_IPLB_NATIVE_DWIDTH 32
#define XPAR_MICROBLAZE_IPLB_BURST_EN 0
#define XPAR_MICROBLAZE_IPLB_P2P 0
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_DP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_M_AXI_DP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_DP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_M_AXI_DP_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_IP_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_M_AXI_IP_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_IP_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IP_PROTOCOL AXI4LITE
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
#define XPAR_MICROBLAZE_D_AXI 1
#define XPAR_MICROBLAZE_D_PLB 0
#define XPAR_MICROBLAZE_D_LMB 1
#define XPAR_MICROBLAZE_I_AXI 1
#define XPAR_MICROBLAZE_I_PLB 0
#define XPAR_MICROBLAZE_I_LMB 1
#define XPAR_MICROBLAZE_USE_MSR_INSTR 1
#define XPAR_MICROBLAZE_USE_PCMP_INSTR 1
#define XPAR_MICROBLAZE_USE_BARREL 1
#define XPAR_MICROBLAZE_USE_DIV 0
#define XPAR_MICROBLAZE_USE_HW_MUL 1
#define XPAR_MICROBLAZE_USE_FPU 0
#define XPAR_MICROBLAZE_USE_REORDER_INSTR 1
#define XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS 0
#define XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION 0
#define XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION 0
#define XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION 0
#define XPAR_MICROBLAZE_FPU_EXCEPTION 0
#define XPAR_MICROBLAZE_FSL_EXCEPTION 0
#define XPAR_MICROBLAZE_USE_STACK_PROTECTION 0
#define XPAR_MICROBLAZE_PVR 0
#define XPAR_MICROBLAZE_PVR_USER1 0x00
#define XPAR_MICROBLAZE_PVR_USER2 0x00000000
#define XPAR_MICROBLAZE_DEBUG_ENABLED 1
#define XPAR_MICROBLAZE_NUMBER_OF_PC_BRK 1
#define XPAR_MICROBLAZE_NUMBER_OF_RD_ADDR_BRK 0
#define XPAR_MICROBLAZE_NUMBER_OF_WR_ADDR_BRK 0
#define XPAR_MICROBLAZE_INTERRUPT_IS_EDGE 1
#define XPAR_MICROBLAZE_EDGE_IS_POSITIVE 1
#define XPAR_MICROBLAZE_RESET_MSR 0x00000000
#define XPAR_MICROBLAZE_OPCODE_0X0_ILLEGAL 0
#define XPAR_MICROBLAZE_FSL_LINKS 0
#define XPAR_MICROBLAZE_FSL_DATA_SIZE 32
#define XPAR_MICROBLAZE_USE_EXTENDED_FSL_INSTR 0
#define XPAR_MICROBLAZE_M0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S0_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S1_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S2_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S3_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S4_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S5_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S6_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S7_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S8_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S9_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S10_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S11_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S12_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S13_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S14_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_S15_AXIS_PROTOCOL GENERIC
#define XPAR_MICROBLAZE_M0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S0_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S1_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S2_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S3_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S4_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S5_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S6_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S7_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S8_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S9_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S10_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S11_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S12_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S13_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S14_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_S15_AXIS_DATA_WIDTH 32
#define XPAR_MICROBLAZE_ICACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_ICACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_USE_ICACHE 0
#define XPAR_MICROBLAZE_ALLOW_ICACHE_WR 1
#define XPAR_MICROBLAZE_ADDR_TAG_BITS 0
#define XPAR_MICROBLAZE_CACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_ICACHE_USE_FSL 0
#define XPAR_MICROBLAZE_ICACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_ICACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_ICACHE_INTERFACE 0
#define XPAR_MICROBLAZE_ICACHE_VICTIMS 0
#define XPAR_MICROBLAZE_ICACHE_STREAMS 0
#define XPAR_MICROBLAZE_ICACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_ICACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_IC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_WRITE 0
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_IC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_IC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_M_AXI_IC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_M_AXI_IC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_IC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_IC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
#define XPAR_MICROBLAZE_DCACHE_BASEADDR 0x00000000
#define XPAR_MICROBLAZE_DCACHE_HIGHADDR 0x3FFFFFFF
#define XPAR_MICROBLAZE_USE_DCACHE 0
#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
#define XPAR_MICROBLAZE_DCACHE_ADDR_TAG 0
#define XPAR_MICROBLAZE_DCACHE_BYTE_SIZE 8192
#define XPAR_MICROBLAZE_DCACHE_USE_FSL 0
#define XPAR_MICROBLAZE_DCACHE_LINE_LEN 4
#define XPAR_MICROBLAZE_DCACHE_ALWAYS_USED 0
#define XPAR_MICROBLAZE_DCACHE_INTERFACE 0
#define XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK 0
#define XPAR_MICROBLAZE_DCACHE_VICTIMS 0
#define XPAR_MICROBLAZE_DCACHE_FORCE_TAG_LUTRAM 0
#define XPAR_MICROBLAZE_DCACHE_DATA_WIDTH 0
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_THREADS 0
#define XPAR_MICROBLAZE_M_AXI_DC_THREAD_ID_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_READ 1
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_WRITE 1
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_NARROW_BURST 0
#define XPAR_MICROBLAZE_M_AXI_DC_DATA_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_ADDR_WIDTH 32
#define XPAR_MICROBLAZE_M_AXI_DC_PROTOCOL AXI4
#define XPAR_MICROBLAZE_M_AXI_DC_EXCLUSIVE_ACCESS 0
#define XPAR_MICROBLAZE_M_AXI_DC_USER_VALUE 0b11111
#define XPAR_MICROBLAZE_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
#define XPAR_MICROBLAZE_M_AXI_DC_AWUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_ARUSER_WIDTH 5
#define XPAR_MICROBLAZE_M_AXI_DC_WUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_RUSER_WIDTH 1
#define XPAR_MICROBLAZE_M_AXI_DC_BUSER_WIDTH 1
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
#define XPAR_MICROBLAZE_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
#define XPAR_MICROBLAZE_USE_MMU 0
#define XPAR_MICROBLAZE_MMU_DTLB_SIZE 4
#define XPAR_MICROBLAZE_MMU_ITLB_SIZE 2
#define XPAR_MICROBLAZE_MMU_TLB_ACCESS 3
#define XPAR_MICROBLAZE_MMU_ZONES 16
#define XPAR_MICROBLAZE_MMU_PRIVILEGED_INSTR 0
#define XPAR_MICROBLAZE_USE_INTERRUPT 2
#define XPAR_MICROBLAZE_USE_EXT_BRK 1
#define XPAR_MICROBLAZE_USE_EXT_NM_BRK 1
#define XPAR_MICROBLAZE_USE_BRANCH_TARGET_CACHE 0
#define XPAR_MICROBLAZE_BRANCH_TARGET_CACHE_SIZE 0
#define XPAR_MICROBLAZE_PC_WIDTH 32
#define XPAR_MICROBLAZE_HW_VER "8.50.b"

/******************************************************************/
 

as you see no ID for interrupt source signal, so can i build interrupt without ID interrupt source ??
 

first thing i run DRC check and got :

WARNING:EDK:4180 - PORT: INTERRUPT, CONNECTOR: Interrupt - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/microblaze_v8_50_b/data/microblaze_v2_1_0.mpd line 412
WARNING:EDK:4180 - PORT: INTERRUPT_ADDRESS, CONNECTOR: Interrupt_Address - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/microblaze_v8_50_b/data/microblaze_v2_1_0.mpd line 413
WARNING:EDK:4180 - PORT: i, CONNECTOR: intc_0_INTERRUPT_Interrupt_Ack - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/intc_v2_00_b/data/intc_v2_1_0.mpd line 25
WARNING:EDK:4180 - PORT: tdi_in, CONNECTOR: bscan_tdi - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 101
WARNING:EDK:4180 - PORT: reset_in, CONNECTOR: bscan_reset - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 102
WARNING:EDK:4180 - PORT: shift_in, CONNECTOR: bscan_shift - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 103
WARNING:EDK:4180 - PORT: update_in, CONNECTOR: bscan_update - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 104
WARNING:EDK:4180 - PORT: sel_in, CONNECTOR: bscan_sel1 - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 105
WARNING:EDK:4180 - PORT: drck_in, CONNECTOR: bscan_drck1 - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 106
WARNING:EDK:4180 - PORT: capture_in, CONNECTOR: bscan_capture - No driver found. Port will be driven to GND - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 107
WARNING:EDK:4181 - PORT: ext_event, CONNECTOR: ext_event - floating connection - /media/mynewdrive/project/_xps_tempmhsfilename.mhs line 37
WARNING:EDK:4181 - PORT: nmi_event, CONNECTOR: nmi_event - floating connection - /media/mynewdrive/project/_xps_tempmhsfilename.mhs line 38
WARNING:EDK:4181 - PORT: irq_in, CONNECTOR: irq_in - floating connection - /media/mynewdrive/project/_xps_tempmhsfilename.mhs line 39
WARNING:EDK:4181 - PORT: INTERRUPT_ACK, CONNECTOR: Interrupt_Ack - floating connection - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/microblaze_v8_50_b/data/microblaze_v2_1_0.mpd line 414
WARNING:EDK:4181 - PORT: req_int, CONNECTOR: intc_0_INTERRUPT_Interrupt - floating connection - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/intc_v2_00_b/data/intc_v2_1_0.mpd line 23
WARNING:EDK:4181 - PORT: vect_int, CONNECTOR: intc_0_INTERRUPT_Interrupt_Address - floating connection - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/intc_v2_00_b/data/intc_v2_1_0.mpd line 24
WARNING:EDK:4181 - PORT: tdo_out, CONNECTOR: bscan_tdo1 - floating connection - /media/mynewdrive/project/ModuleSearchPath/archived_ip_repository/ProcessorIPLib/pcores/chipscope_icon_v1_06_a/data/chipscope_icon_v2_1_0.mpd line 108

so from first impression it seems to me that your interupts are not connected at all, and wired to GND.
 

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