kansagaratushar
Newbie level 5
- Joined
- Jan 7, 2013
- Messages
- 8
- Helped
- 1
- Reputation
- 2
- Reaction score
- 1
- Trophy points
- 1,283
- Activity points
- 1,338
Hi,
I know how to use inout signals in systemverilog simple testbench. But How can I use inout signals in UVM testbench Environment?
In which class Should I define & drive another "reg" signal with control variable.....?
How can I define in interface and Top module?
Any Help are thankful to me.
I know how to use inout signals in systemverilog simple testbench. But How can I use inout signals in UVM testbench Environment?
In which class Should I define & drive another "reg" signal with control variable.....?
How can I define in interface and Top module?
Any Help are thankful to me.