How to use hspice's debug information?

If hspice simulation stops by nonconvergence problem, a list of debug nodal voltage is printed out. Any one know how to use these informations to sove nonvergence problem?

.ic or .nodeset for setting the initial conditions of some of the critical nodes.

I know that nonconvergence problem can sometimes be solved by setting initial conditions by .ic or .nodeset statement. But I don't know what initial conditions shoud be set. In a large circuit, initial conditions are diffult to calculate by hand. Is it possible to get some clue from the hspice's debug informations?

I've suffered this before, and it has been solved by doing the following hints.
For your case, maybe you can try
1) .OPTION CONVERGE=1 GMINDC=1.0000E-12
2) change global power statement as ramp one.
ex.
vx avdd 0 pwl (0ns 0v 1ns 0v 2ns 'vhi')
*vx avdd 0 dc 'vhi'
vz vdd 0 pwl (0ns 0v 1ns 0v 2ns 'vhi')
*vz vdd 0 dc 'vhi'

Please also refer to this link to get more information.

**broken link removed**

"timestep too small"-- Transient Convergence Problem:

Solution:
0. Check circuit topology and connectivity.
This item is the same as item 0 in the DC analysis.

1. Set RELTOL=.01 in the .OPTIONS statement.
Example: .OPTIONS RELTOL=.01

2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
Example: . OPTION ABSTOL=1N VNTOL=1M

3. Set ITL4=500 in the .OPTIONS statement.
Example: .OPTIONS ITL4=500

4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.

5. Reduce the rise/fall times of the PULSE sources.
Example: VCC 1 0 PULSE 0 1 0 0 0
becomes VCC 1 0 PULSE 0 1 0 1U 1U

6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
Example: .OPTIONS RAMPTIME=10NS

7. Add UIC (Use Initial Conditions) to the .TRAN line.
Example: .TRAN .1N 100N UIC

8. Change the integration method to Gear (See also Special Cases below).
Example: .OPTIONS METHOD=GEAR

Regards,

Thanks, shiowjyh. My circuit is suffering from AC nonconvergence, so some of the above-mentioned solutions are not applicable. I tried almost all the other solutions, yet the problem could not be solved.

The circuit is a three-stage CMOS amplifier. If I broken the connection the first and the second stage, convergence is OK. Since the inputs of the second do not draw DC currents, so I think the operating point do not change when connections between the first- and second-stage are broken. Then I connect the circuit again and use ".IC" statement to set the initial conditions of these two nodes (inputs of the second stage), using the values got from the previous simulation. What do you think about my solution? Is there something wrong? Thank you.

You beat me, Hughes!!
I am not quit sure what you were doing is right; however there is many ways to do ac analysis.
There shall be a new question comes out; does my ac analysis doing right? I've ever got two different dc gain & phase margin using two methods.
For AC convergence problem, I found a topic that you might interest.
Please refer to the following link, and see it worth or not!

**broken link removed**

Regards,

what kind of amplifier? 3 stage, yes, but single ended or diferential input?

What about the expected gain?

change ITL parameters in the .option to let the simulator make more iteration cycles.

Does simulation stops during the actual AC sweep or during the previous bias point determination?

Do you have a .OP statement?

Try also GRAMP in the .option

To obtain the initial conditions, make a transient analysis and use .SAVE at at given time. The use .LOAD to initialize the circuit at (or near) its operating point.

Thanks. My design is a three-stage differential-input single-output general purpose op amp. The expected gain is 130dB or more, the unit-gain bandwidth ~5MHz.

The nonconvergence problem occurs during operating point calculation. It contains a .OP statement. I find it is hard to convergence in open-loop. The nonconergence problem was solved when the op amp was in a closed-loop application (1000x amplifier). But I don't know whether open-loop characteritics can be derived from closed-loop characteristics.

Thanks angain. I will try your recommends later. I will post the solution if the nonconvergence problem is solved.

The non-convergence problem is a headache, I agree.
There is too much possibility of the causes.

I think you can add something inside .option maybe itol so that the noncovergent stop one by one to the one you need to fix. check with hspice manual

Generally, i did a tran simulation first.
Then save the operation point value when the amplifier is in amplifying.
Use .ic to load those initial values.
At last, i can perform the AC analysis.

But if the circuit is still no convergence, u may change gmindc value to 1e-10, 1e-9 or even 1e-8...

Hope this can help.

a book , inside spice , you can reading ..

and use pwl power supply or change time step also can solve .tran ..
non-convergence ..

by the way , some .option command can convergence but maybe have
fake simulation report

markty is right!