you need to convert the 12 bit integer to floating point in a convert block. why do you need floating point anyway? fpgas work better with fixed point.
Well Floating point is difficult to deal with as TrickyDicky said
I too was working on it and every time I had to change a little logic or found a little change to be made in my program, I find it hectic,
So I quit the idea and hence fixed point worked well...
Any ways you can find the difference between the two using googlesince there is lots of stuff present.
With regards to converting converting your input to 32 bit you can concatenate 20 ZEROS on the MSBs ( verilog has concatenating and replicating function, utilize it). But even then it
will not be a floating point rather a fixed point number, you have to completey change your number to floating point using fixed-to-floating pt IP
Well I dont have much idea of VHDL since I work on verilog,
Yes to me it is the good idea of converting floating point to fixed point. Well in fix-point if you should know how many bits you have for integer and how many for fraction in your design.
This way you should decide your operation. e.g. if you have no fraction point than no need to worry at all just multiply like normal operation else you have to manipulate little things
either before or after operation ( can't think of now...all mention in the link I have given )
You have better understanding reading **broken link removed**
Cheers
Shan
Currently I have to use the numbers like 0.1, 6.51E-5 and such as my multplier/comparator therefore I have to do fixed to float and then float to fixed as the output...but I was wondering, can I directly convert my 12-bit signal into a floating-point since it's possible to customize the integer width and fraction width...for example I assign 12 for the integer width and 0 for fraction width...
Floating point is not simple. You HAVE to use the floating point IP blocks for conversion and arithmatic, because they have a high latency and large resource usage. Fixed point on the other hand is the same as integer maths, so has very low latency and uses very little resources.
0.1 and 0.000065 can easily be done in fixed point. You just need to make sure you chose enough bits to cover the smallest fractions.
Floating point is not simple. You HAVE to use the floating point IP blocks for conversion and arithmatic, because they have a high latency and large resource usage. Fixed point on the other hand is the same as integer maths, so has very low latency and uses very little resources.
0.1 and 0.000065 can easily be done in fixed point. You just need to make sure you chose enough bits to cover the smallest fractions.
No conversion necessary. You just need to keep track of the integer and fraction parts and make sure you have the bits aligned properly.
well you have to make sure you always zero pad the right direction.
If you know you have a 2.2 unsigned number
"11.01" = 3.25 (13 in integer)
and 3.1 number:
"110.1" = 6.5 (13 in integer)
If you simply add, without tracking the separation, you get
"11010" = 26
Which is incorrect. You need to zero pad the numbers
"01101" + "11010" = "1001.11" = 39 integer = 9.75
There is a VHDL package which takes care of all this for you. www.vhdl.org/fphdl
Otherwise you have to track this zero padding and integer/fraction separation manually in your code.
yes, you still need std_logic_1164. That is the base type all the fixed point types are based on.
You need to include the source code in your project.
---------- Post added at 13:53 ---------- Previous post was at 13:52 ----------
Im not a Xilinx person so cant really help with ISE much - sorry.
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages..
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 1.21 $
-- Date : $Date: 2007-09-11 14:52:13-04 $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
dont simply copy/paste the code. add the files on their own
The error you get is because you didnt include std_logic_1164 package
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.ALL;
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;
you didnt actually say where the error pointed to. but it sounds like you've copied and pasted this code into your file. don't.
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