How to use delay in a design using VHDL/Verilog?

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dinesh.4126

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Hi,
As we know that in verilog or VHDL delay are non syntesiable only they we use in writting the test bench ,so if want to use delay in our design then how we can use
it.

THANX.
 

Re: Delay Concept

dinesh.4126 said:
Hi,
As we know that in verilog or VHDL delay are non syntesiable only they we use in writting the test bench ,so if want to use delay in our design then how we can use
it.

THANX.
Click to expand...
Buffer insertion introduces delays.
 
Re: Delay Concept

dinesh.4126 said:
Hi,
As we know that in verilog or VHDL delay are non syntesiable only they we use in writting the test bench ,so if want to use delay in our design then how we can use
it.

THANX.
Click to expand...

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If you feel I have helped you, please click the helped me button.

Thanks,

all the best.
 
Re: Delay Concept

Use a simple counter (std_logic_vector) to count clock edges. First calculate the time period of a clock cycle and how much delay you require. From this data, you can calculate how many number of clock edges (either positive or negetive, but not both) you need to wait (or count) for providing the required time delay.

implement the same in a process block.
 

Delay Concept

Well, it depends how much delay you would like. In a synthesizeable design its not possible to have a definite delay inserted when the delay value is less than 1/2 the clock period of the clock you are using. Using buffers will give you a delay, but the delay value will not be deterministic. Well, if you would like to have a delay of more than 1/2 a clock period, then you can use a counter to implement that, or if the delay is just 1 or 2 clock periods, then just pass the signal throuth 1 or 2 D flip flops respectively. Hope it helps,
kr,
Avi
 

Re: Delay Concept


Now i need a delay of exactly 1/2 of clock period. Input clock is 40MHz. This gives a time period of 25ns. I nees a delay of 12.5ns !!. Any idea how to achieve that?
 

Generate a clock from PLL of 80MHZ from your input clock(40 MHZ), The newly generated clock will have 12.5ns clock period and that matches your delay requirement.

This is one of the method, if it is a smaller delay, would have gone with buffer insertion.
 

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