module phase_freq_sel(
input dcm_clk_in,
input p_sel0 ,p_sel1,
input f_sel0 , f_sel1,
output fpga_clk,
output clk_90,clk_180, clk_270,
output reg slctd_phase,
input rst,
output reg Out_div_2,
output reg Out_div_4,
output reg Out_div_8,
output reg slctd_freq);
always@(posedge slctd_phase) ///// i Have error here, this is my output from dcm, how to use this output as an input here???
begin
if(rst)
Out_div_2 <= 1'b1; else
begin
Out_div_2 <= ! Out_div_2;
end
end
always@(posedge Out_div_2)
begin
if(rst)
Out_div_4 <= 1'b1;
else
begin
Out_div_4 <= ! Out_div_4;
end
end
always@(posedge Out_div_4)
begin
if(rst)
Out_div_8 <= 1'b1;
else
begin
Out_div_8 <= ! Out_div_8;
end
end
always@( f_sel0 or f_sel1 or Out_div_2 or Out_div_4 or Out_div_8 )
begin
if(f_sel1 == 0 && f_sel0 == 0) slctd_freq = Out_div_2;
else if(f_sel1 == 0 && f_sel0 == 1) slctd_freq = Out_div_4;
else if(f_sel1 == 1 && f_sel0 == 0) slctd_freq = Out_div_8;
else slctd_freq = 1'bx;
end
// Instantiate the module
dcm_fixed_phase dcm (
.CLKIN_IN(dcm_clk_in),
.RST_IN(rst),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(fpga_clk),
.CLK90_OUT(clk_90),
.CLK180_OUT(clk_180),
.CLK270_OUT(clk_270)
);
always@( p_sel0 or p_sel1 or clk_90 or clk_180 or clk_270 )
begin
if(p_sel1 == 0 && p_sel0 == 0) slctd_phase = clk_90;
else if(p_sel1 == 0 && p_sel0 == 1) slctd_phase = clk_180;
else if(p_sel1 == 1 && p_sel0 == 0) slctd_phase = clk_270;
else slctd_phase = 1'bx;
end
endmodule
Here is my code. I am trying to design so that i have a selected phase and a selected freq at output. 1st i select phase which is OK then i use that slected phase as an input to freq selector. I am using TFF for the freq selection. When i give selected phase as an input to TFF. My outputs are unknown.. How to use DCM output as an input for another logic???