how to use assert to verify the clock width in VHDL?

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yanzixuan

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I try this:
Code:
  assert rising_edge(clk_osc_C) and clk_osc_C'last_event >= 10 ns
        report "the width of clk_osc_C is too narrow"
        severity ERROR;

bu failed, can any body give me some suggestion?
 

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