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How to ungroup a design while preserving the full path of instances (dc_sehll)?
Dear all,
I am looking for a way to ungroup my design during synthesis flow while keep the full path of the intances. For example assume that I have:
module sparc();
div div0 ( )
endmodule
now when I use: compile -ungroup_all
it ungroup all the design and give sth like:
module sparc();
U1 nand2 ...
U2 and2 ....
U3 or ...
endmodule
but I need to keep the exact path of the intances such as
module sparc();
div0/U1 nand2 ... ----------------> In this way (div0/U1) I can find that nand2 belongs to module div0 even when the whole design is ungrouped.
U2 and2 ....
U3 or ...
endmodule
Thanks a lot
Dear all,
I am looking for a way to ungroup my design during synthesis flow while keep the full path of the intances. For example assume that I have:
module sparc();
div div0 ( )
endmodule
now when I use: compile -ungroup_all
it ungroup all the design and give sth like:
module sparc();
U1 nand2 ...
U2 and2 ....
U3 or ...
endmodule
but I need to keep the exact path of the intances such as
module sparc();
div0/U1 nand2 ... ----------------> In this way (div0/U1) I can find that nand2 belongs to module div0 even when the whole design is ungrouped.
U2 and2 ....
U3 or ...
endmodule
Thanks a lot
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