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how to understand this high speed clock driver circuit?
This circuit is from the book "Scientific charge-coupled devices".
It seems much hard to understand.
Well, it looks like a bit of a kluge of older technology. Transistors have trouble turning on and turning off quickly. So you can use ac coupled circuits in parallel to force charge into or out of the bases to speed things up.
I can not understand the two capacitors!
can any nice guy explain in detail?
can any nice guy give some other circuit structure to implement the same function?
When one of terminal of capacitor is changed from high to low quickly, the another terminal will be coupled from high to low too.
In principle, the voltage between two terminals of capacitor will not change immediately.
Leo_o2's expalnation is pretty good - except that when the input goes HIGH, Q4's base is pulled low and the o/p is LOW, i.e. the ckt is inverting - BUT when the input goes low the o/p goes high for a limited time only as there is no DC path to keep the o/p high, thus a square wave input will give an inverted o/p with shorter positive pulses. The 330pF caps speed up the switching times. The RC on the o/p sets the slew rate of the output edges.
Hope this helps, regards, Orson Cart.
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