How to transform VHDL code to Spice netlist?

[etherios]

VHDL to Spice

CAn i transform VHDL code to spice netlist?

 

[gerryhsu]

Re: VHDL to Spice

what level of VHDL? In general, the answer is No.

 

[geconom]

Re: VHDL to Spice

Usually you need a synthesis tool to go from HDL to EDIF. EDIF + cell library can be automatically layed out and extracted as a spice netlist.

 

[okguy]

Re: VHDL to Spice

To make a spice netlist, you need at least spice netlist for all your digital library cells. Then, you need a gate level netlist.
Then, you may expect to produce a spice netlist.

Then, some ways :
- produce a CDL netlist (spice compatible ... some text processing may be needed), Cadence can probably do it
- Nassda has a tools called v2s to transfer verilog to spice, so you may first have to transfer from vhdl gate netlist to verilog gate netlist
- write your own perl script