[SOLVED] How to trace the original of netlist gates back to the original RTL description

[noureddine-as]

When an RTL circuit is synthesized for an ASIC technology, is to possible to trace back the original source code of the generate netlist gates?

More specifically, I compiled an RTL IP using Design Compiler, and then I studied its power consumption in PrimeTime. But I saw that some modules are consuming strangely bigger than they should. However, I could not trace back to the root cause of this power consumption, since this happens to be in the leaf cells. Is there a way to trace back these leaves to the original RTL source code?

 

[ThisIsNotSam]

When an RTL circuit is synthesized for an ASIC technology, is to possible to trace back the original source code of the generate netlist gates?

More specifically, I compiled an RTL IP using Design Compiler, and then I studied its power consumption in PrimeTime. But I saw that some modules are consuming strangely bigger than they should. However, I could not trace back to the root cause of this power consumption, since this happens to be in the leaf cells. Is there a way to trace back these leaves to the original RTL source code?

not really. this would be reverse engineering, and while a lot of research has been done on this topic, there is no push-button solution for it.

however, in your case, you have the rtl and the netlist. you just need to use your engineering skills. you can have synthesis keep the hierarchy instead of ungrouping everything, this would help you visualize where the gates belong to.

 

[noureddine-as]

Okay ThisIsNotSam, that's what I do for know. The problem I had is with the leaf cells generated from the assign statements and muxes and stuff like that.
I'm working this around by isolating each part in a separate module in order for its consumption to be visible in the PrimeTime Power hierarchical reports.

Thanks fo the information anyway!

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not really. this would be reverse engineering, and while a lot of research has been done on this topic, there is no push-button solution for it.

however, in your case, you have the rtl and the netlist. you just need to use your engineering skills. you can have synthesis keep the hierarchy instead of ungrouping everything, this would help you visualize where the gates belong to.

Do you if there are any way to label particular statements (for example assign) in SystemVerilog? Or any other way to generate an additional hierarchy level other than using modules would do the trick.

I tried for example dummy generate like the following, but obviously it gets optimized away by DC.

  genvar i;
  generate
      for (i = 0; i < 1; i++) begin : label
          assign output = Some_Logic_Op_Here ;
      end
  endgenerate
[\CODE]

 

[ThisIsNotSam]

Okay ThisIsNotSam, that's what I do for know. The problem I had is with the leaf cells generated from the assign statements and muxes and stuff like that.
I'm working this around by isolating each part in a separate module in order for its consumption to be visible in the PrimeTime Power hierarchical reports.

Thanks fo the information anyway!

- - - Updated - - -



Do you if there are any way to label particular statements (for example assign) in SystemVerilog? Or any other way to generate an additional hierarchy level other than using modules would do the trick.

I tried for example dummy generate like the following, but obviously it gets optimized away by DC.

  genvar i;
  generate
      for (i = 0; i < 1; i++) begin : label
          assign output = Some_Logic_Op_Here ;
      end
  endgenerate
[\CODE][/QUOTE]

this analysis is so fine grained, it's hard to think why one owuld need to understand the power consumption of a handful of cells when a modern IP has 1M+ cells.

 

[noureddine-as]

this analysis is so fine grained, it's hard to think why one owuld need to understand the power consumption of a handful of cells when a modern IP has 1M+ cells.

No, what I mean is that, In the IP (which is actually a floating-point unit) there are a lot of arithmetic stuff .. and it's all combinational. So when it's synthesized you no longer no what comes from where .. so I want design compiler to label the names of the cells instances somehow, sow I can have an intuition about where they would come from.

Again I'm beginner in HW/ASIC dev, but I'm exploring the possibilities .. Thanks for the ideas!

 

[ThisIsNotSam]

I don't know if there is a way to achieve what you want. I am leaning to say no, there isn't. If you really need this analysis, you can create a more fragmented hierarchy and force the tool not to ungroup anything.

 

[FvM]

Did you try to synthesize with different optimizer goals and timing constraints? A possible reason for increased power consumption could be that the synthesizer is duplicating gates to achieve timing constraints.