how to test the "input leakage current" of schmitt

After designed my shmitt trigger, I need to guarantee its input leakage current is below 0.1uA. However, I have no idea of doing that. Anybody can give me a clue? Thanks a lot.

Re: how to test the "input leakage current" of sch

Hi,

Depending on your level of design (student proj. vs. production design) there are several cases I can think of:

1) Simple Schmitt trigger: Run simulation with input at Vin(min) and Vin(max), measure current through the input voltage source, across process/voltage/temperature. For CMOS process, input current should be Zero.

2) Schmitt trigger for product design: Estimate leakage current of ESD protection circuits by modelling the diode area. Run same simulation across proc/volt/temp; however, be sure to correlate results with wafer data, as diode leakage is rarely modelled correctly over temperature.

3) Schmitt trigger for production parts: Submit parts to an ESD tester, zap them to the spec on ESD model (HBM or Machine). Then measure leakage across temp.

Hi dipswitch,

I think the first one is what I am looking for. Thanks.

BTW, Sometimes, we also setup the input voltage around the trip point of the schmitt trigger to test the biggest current (current spike) flows through the upper two pmos transistors, correct?