Matrix_YL
Advanced Member level 4
HI all
I waste too much LUTS in my chip! so I want to use my block_ram resource.Is there any ways to synthesize a shifter in BlockRam of XILINX's FPGA!
how set my EDA tools (Synplify 7.5) or add some attributes to complete it!
my device xcv50bg256-6.
verilog and vhdl are all best needed !
thank you !
I waste too much LUTS in my chip! so I want to use my block_ram resource.Is there any ways to synthesize a shifter in BlockRam of XILINX's FPGA!
how set my EDA tools (Synplify 7.5) or add some attributes to complete it!
my device xcv50bg256-6.
verilog and vhdl are all best needed !
thank you !