How to stop the simulation in VHDL TB

CLK_GEN: process
begin
		 
	if ENDSIM=false then
		CLK <= '0';
		wait for CLK_PERIOD/2;
		CLK <= '1';
		wait for CLK_PERIOD/2;
	else
		wait;
	end if;		
end process;
		
STIM: process
begin
	-- your stim
	ENDSIM := true;
	wait;			
end process STIM;

library std;
use std.env.all;

.......
stop(0);
--or
finish(0);

-- For both STOP and FINISH the STATUS values are those used
  -- in the Verilog $finish task
  -- 0 prints nothing
  -- 1 prints simulation time and location
  -- 2 prints simulation time, location, and statistics about
  --   the memory and CPU times used in simulation

  -- Other STATUS values are interpreted as 0.

clk_process :process
        begin
          for Z in 1 to 800000
          loop
            clk  <= '1'  ;
            wait for 5 ns; -- half period
            clk  <= '0'  ;
            wait for 5 ns; --half period
         end  loop;
          wait;
        end process;

stop_simulation :process
begin
	wait for 100 ns; --run the simulation for this duration
	assert false
		report "simulation ended"
		severity failure;
end process ;

------------------------------------------------------------------------------------------------
  --clk_proc : process to generate the clock
  ------------------------------------------------------------------------------------------------
  vid_clk_proc : process
    variable end_time       : time;
  begin
    while not ENDSIM loop
      
      clk                    <= not clk;
      
      if NOW >= TIMEOUT*CLK_PERIOD then
        KILLSIM               <= true;
      end if;
      
      if run_clk then
        wait for CLK_PERIOD/2;
      else
        wait until run_clk;
      end if;
    end loop;
    
    if KILLSIM then
      report "Simulation Timed Out after " & integer'image(TIMEOUT) & " clock cycles."
        severity warning;
        
    else
      end_time := NOW;
      
      report "Simulation ended successfully after " & time'image(end_time)
        severity note;
        
    end if;
    
    wait;
  end process;
  
  -------------------------------------------------------
  --Initial reset to setup all registers and memories
  -------------------------------------------------------
  reset <= '1', '0' after RESET_PERIOD*CLK_PERIOD;
	
	
  --------------------------------------------------------------------
  --Stop all processes to starve all events and stop the simulation
  --------------------------------------------------------------------
  ENDSIM <=    KILLSIM 
            or (input_complete and output_complete);