HOw to split bus in FPGA Adv using "Block Diagram' ent

[always@smart]

add bus with a ripper

Hi all,

I could not manage to split the bus using FPGA Advantage in the "Block Diagram" entry. Below is an example

----------------------------------------------------------
module aaa0(a0,.......);
input a0[7:0];
.........

endmodule

----------------------------------------------------------
module aaa1(a1,......)
input a1[7:0];

endmodule

----------------------------------------------------------

I wanna to split the bus to be like:

module top(A,.....)
input A[15:0];
aaa0 (.a0(A[7:0]),.......);
aaa1(.a1(A[15:7]),.......)


endmodule
----------------------------------------------------------

when I tried to connect the A to both a0 and a1, both a0 and a1 have become a0[15:0] and a1[15:0], so how can I change them to a0[7:0] and a1[15:7]??

Thank you in advance

 

[Ace-X]

fpga advantage bus ripper

Just double-click on bus and in Window "Object Properties" select desired Slice/Index.

Good luck!

Ace-X.

 

[dll_embed]

Re: HOw to split bus in FPGA Adv using "Block Diagram'

Use the button "Add bus with a ripper". It is designed for it.

 

[always@smart]

Re: HOw to split bus in FPGA Adv using "Block Diagram'

Hi dll_embed,

THank you for your help, now I manage to chage the bus with the method you have suggested, it is so simple.

1. click the "Adds a Bus with a Ripper" and route the top-level bus, then double click the bus and change the properties accordingly to the top-level bus width, example : A[15:0].

2. secondly, click "Adds a Bus with a Ripper" again, route it then change the bottom-level bus width, example : a[7:0]



Regards,
Always smart