How to specify the Vcom voltage of sigma delta modulator

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BackerShu

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reltol vabstol sigma delta

Hi, everyone. A question about specifying the 2rd sigma delta modulator bothers you.
The modulator that I chose is shown in Fig 1:

Here are somethings about the amplifer(or integrator) and comparator. The supply voltage of the modulator is 1.8V
Amplifiers: the input common mode voltage is 0.7V,and the output voltage range is 0-1.4v. The integrator's gain is 1/2. The two stages integrator works well when I set Vcmi 0.7v and using 0v to substitute the feedback voltage Vref+ and Vref-.
Comparator: It works well on the sample clock 6.4MHz.
At last, I connect the all the parts to check whether the modulator works. The feedback circuit I design is shown in Fig2.

Where R and S are the output of the comparator,S2 and S2b are the clock signal,and symbol TG is a simple CMOS switch.
In the simulation, I set Vref+ 1.4v,Vref- 0v and Vcmi 0.7v.But the modulator's performance isn't right.I think the problems may lie in this two aspects.
1) I set the wrong value of Vref+ Vref- and Vcmi
2) The feedback that I decide isn't suitable for the modulator.
Please help me! Thank you in advance!

Regards!
BackerShu
 

hi BackerShu,

the transistor connected to Vref+ should be pmos, otherwise nmos always cut off.

your setting of Vref+, Vref- and Vcmi is right.
 

Hi jiangxb

R and S are the outputs of the SR latch after the comparator. They are contrary. In my opinion, When S is 1, the feedback voltage should be Vref+, otherwise Vref-. So I think the transistor connected to Vref+ should be nmos. And the feedback voltage tranfered by TG when the clock S2 is enable. Am I right?
If it's wrong, I should have some misunderstanding of how the feedback circuit of the modulator works. Can you explain it to me more particularly. Thank you very much!

BackerShu
 

hi BackerShu,

yes, you are right. but nmos can't be used to transfer high voltage, so substituting nmos connected to vref+ by pmos and controlling it's gate by R.
 

Hi jiangxb.
Sorry for my late reply! I have changed the feedback circuit as you suggested,and it works better than before. Thank you very much!

Another question to bother everyone!Fig 1 shows the simulation results of the 2rd Sigma Delta modulator.

Where the Outn and Outp are the negtive and positive outpue of the second integrator,S is the output of the SR latch after the comparator,and Vin+ is the input signal.I think the result isn't right,because
1)the glitch of Outn and Outp are too large
2)S and Vin+ are not under the correct relationship as the princple of the 2rd modulator.
Please tell me where the promble may lie in my circuit. THank you!

PS:I don't know if I have give out enough information for you to help me. You can ask me to show the any information about the circuit and the simulations you want.
 

hi BackerShu,

yes, the results seem to incorrect. i suggest simulating the modulator using ideal opamp. then uploading the modulator and simulation results.
 

I wanted to use the ideal opamp. But I cann't find a fully differential opamp in my cadence tools. What can I do to find an ideal fully differentiao opamp?

In the other hand, I tried to do some simulations to demonstrate that the opamp that I designed can meet the need of the modulator. Fig 1 is the output of the two stages integrator by 200mv sine input signal.



Anythings else I could do to check if the opamp is suitable?Thank you!

Regards!
 

I use the ideal opamp in hspice by vcvs and i think there is an ideal opamp like vcvs in cadence, too.
Visit the following for more details.
 

hi BackerShu,

construct ideal fully-differential opamp using vcvs and voltage source as below. the voltage gain of E1 and E2 is 10000 or more.
 

Hi jiangxb.
I constructed a ideal fully opamp according to the graphic you showed above and set thevoltage gain of the E1 and E2 at 100000. The opamp works well.But when I use it to substitute the opamp that I designed, an error turned out. It says that the tran simulation is no convergence. I tried to make it convergence, but I failed. Fig 1 is the results before the error happened.Fig 2 is the discription of the error.

Added after 36 minutes:


 

hi BackerShu,

in general the cause of no convergence is various and complex, firstly you should check your circuit ensuring it's correct, secondly you can adjust some simulation setting, for example loosing convergence criteria, i.e. reltol, vabstol and iabstol, or increasing gmin, or changing integration method to gear2, etc..

from your simulation results i think maybe the reference feedback is inverse, change feedback polarity and try again.
 

Hi jiangxb!

I check the circuit carefully and make sure that it is correct according to the structe of the modulator that I upload before.

Also I tried to loose the convergence criteria and turned the integration method to gear2. But the problem still can't be overwhelmed.

Something suggested that there may be something wrong with the ideal opamp that I constructed.Fig 1 is the ideal opamp that I constructed.

when I put it into an one stage integrator(Fig 2),the simulation is convergence,but the result showed in Fig 3 is not right comparing to the result(Fig 4) that I got using the opamp that I designed.





I have been looking for the reason the whole day. But got nothing useful. Fig 6 is the settings of the vcvs in the ideal opamp. Is there something wrong?


Regards！
 

hi BackerShu,

you have constructed incorrect ideal opamp differing from one i provided. vin+ and vin- is inverse. the minimum and maximum voltage of vcvs should be set to -0.7V and +0.7V.
 

Hi jiangxb.

The ideal opamp works well now and the circuit is convergence. But the simulation result of the 2rd modulator consisted of the ideal opamp and the comparator that I designed show in Fig 1 isn't right yet.

V11+ and V11- is the node between S1 and C1 in the structure of the modulator I upload above. There're so many glitchs at these two nodes.But V11+ -V11- seems to be right. And the comparator also seems to work well. But the final result S is not the alternation of 1 and 0 in every cycle as we expected. I can't figure out the reason. Things seem to be all right without the final result. Where may the problem lies in? Thank you!

PS:the frequency of the input signal is 25KHz,and the sampling rate is 6.4MHz.
 

hi BackerShu,

can you upload the expanded figure so i can identify voltage transient in one clock phase, and include more results such as input and output of each opamp?
 

Hi jiangxb

Thank you!
Fig 1 the schematic of the 2rd modulator

Fig 2 the clock for the circuit(Sxb is the invertion of Sx)

Fig 3 and 4,the results


Fig 5 and 6,the expanded figure of Fig3 and 4

 

hi BackerShu,

how much is the capacitance of each capacitor in modulator? which paper have you referred to?
 

Hi jinagxb

The sample capacitor is 2.5pF, and the feedback capacitor is 5pF, in the two integrators.
 

the structure of the modulator is from the paper.But the specification isn't the same. In my design, the oversample rate is 128(fin=25KHz,fs=6.4MHz).
 

hi BackerShu,

maybe the cause is saturation of integrator. decrease feedback reference voltage, for example, vref+ 1.05V and vref- 0.35V, and try again.
 

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