How to specify the design in CADENCE GENUS?

[prabhath_pes]

I have been working on openMSP430 microcontroller. The design is consists of so many modules including execution unit, program memory, hardware multiplier, etc.
Now I need to do synthesis. I have elaborated the design successfully. But I'm getting error when I read sdc file. The tool pops up a message that "Multiple designs are available. Specify the design you want to use. [TUI-17] [::dc::get_ports]".

How to specify the top module design? The name of the top module verilog file is openMSP430.v .

Can somebody tell?

 

[ThisIsNotSam]

it means you are reading some files that are not present in the hierarchy, so the synthesis tool complains that it doesn't know which "top" to use. you should probably revise the list of files you are passing to the tool, something shouldn't be there.

 

[wizard]

I have been working on openMSP430 microcontroller. The design is consists of so many modules including execution unit, program memory, hardware multiplier, etc.
Now I need to do synthesis. I have elaborated the design successfully. But I'm getting error when I read sdc file. The tool pops up a message that "Multiple designs are available. Specify the design you want to use. [TUI-17] [::dc::get_ports]".

How to specify the top module design? The name of the top module verilog file is openMSP430.v .

Can somebody tell?

You need specify top name for elaborate command if there are multiple tops in your provided RTL.