how to solve spurs of Freqency synthesizer design

during designing Frequence synthesizer ,I faced some questions,and I dont know how to do next .
I use LMX2320TM+loop filter+VCO(Korea's Sangshin company KSV-5M1843), other parameters as followings:
frequence oscillator: 12.8MHz
phase detector Freq: 200KHz
R value:64
prescaler:64
VCO RFout :1843MHz
loop filter:C1＝240PF，C2＝1.5nF,R1=20K,R2=130K,C3=13PF (by your EasyPLL )
loop filter bandwidth: 12KHz
test results see annex
Main questions is spurs , I don't know how to solve them! please help
me !!!

during designing Frequence synthesizer ,I faced some questions,and I dont know how to do next .
I use LMX2320TM+loop filter+VCO(Korea's Sangshin company KSV-5M1843), other parameters as followings:
frequence oscillator: 12.8MHz
phase detector Freq: 200KHz
R value:64
prescaler:64
VCO RFout :1843MHz
loop filter:C1＝240PF，C2＝1.5nF,R1=20K,R2=130K,C3=13PF (by your EasyPLL )
loop filter bandwidth: 12KHz
test results see annex
Main questions is spurs , I don't know how to solve them! please help
me !!!

during designing Frequence synthesizer ,I faced some questions,and I dont know how to do next .
I use LMX2320TM+loop filter+VCO(Korea's Sangshin company KSV-5M1843), other parameters as followings:
frequence oscillator: 12.8MHz
phase detector Freq: 200KHz
R value:64
prescaler:64
VCO RFout :1843MHz
loop filter:C1＝240PF，C2＝1.5nF,R1=20K,R2=130K,C3=13PF (by your EasyPLL )
loop filter bandwidth: 12KHz
test results see annex
Main questions is spurs , I don't know how to solve them! please help
me !!!

Hi,

You can reduce the BW of loop filter or increase the freqeuncy of reference clock so that the loop filter can cut the ref. clk singal.

The ref. spur is come from the leakage of ref. clock to the charge pump of PLL.

You also can consider to use a 3rd order loop filter instead of 2nd order loop filter.

Yakult

:!: :?
To reduce a spurius level you need better loop filter 3 order. If still spurius exist reduce loop bandwidth . If problem still exist take care about PCB layout for tunning voltage VCO it is necessary to be short as possible. IF still problem exist divide power supply voltage which coming to PLL IC and VCO wit aditional RC filters (small R and big C 5.6OHm and 10-100uF)

GL XTASA

I noticed that in the above design, the loop filter is already 3rd order.
For integer-N frequency synthesizer, the spurs occur at frequencies (and it's harmonics) of the PFD. This is because the outputs of the PFD turn on and off the charge pump at the same frequency. So you can increase the PFD frequency to move the spurs away from the carrier. But if the frequency resolution is 200KHz, then you should use fractional-N architecture, then you can use 13MHz (or 26MHz) PFD frequency (these are industry standard) and not lose the frequency resolution.
But in fractional-N architecture, the spurs at the PFD frequency and it's harmonics run away, there are other spurs named fractional spurs. Then using some noise shaping method -- delta-sigma modulator to control the main divider to push the fractional spurs to higher frequencies.

I assume you have done your calculations correctly and the loop has good phase margin > 45 degrees.

The high value of R2 will make the junction of R2/C3 a very sensitive node. I assume this node is connected to the VCO tune line. R2/C3 should be placed right at the VCO. If you place them near the other loop components and then run a long line to the VCO, you will find the PLL has great sensitivity to spurs.

i think c3 is too smaller ,it should be greater than the capacitance of the vt.

thank you very much!

I have solved this question!

1) I changed the loop bandwidth from 12KHz to 6KHz.
2) power supply voltage of VCO is decoupled!

myicejade said:

thank you very much!

I have solved this question!

1) I changed the loop bandwidth from 12KHz to 6KHz.
2) power supply voltage of VCO is decoupled!

Click to expand...

Would you please tell me what do you mean
by decouple the supply of VCO (use inductor connect

supply ??) Thx

I mean that the supply power for VCO is decoupled sufficiently by by-pass capacitor and electrolytic capacitor.