how to solve latch problem:

hi anyone

in my project when exchange this statements:



with ir(3 downto 1) select
output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result when "000",
variance_result when "001",
st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result when "010",
rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result when "011",
covariance_result when "100",
mse_result when "101",
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ" when others;



by :



process(ir,mean_result,variance_result,st_dev_result,rms_result,covariance_result,mse_result)
begin
case ir(3 downto 1) is
when "000" =>output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result (16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result (16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result;
when "001" =>output<=variance_result;
when "010" =>output<=st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result;
when "011" =>output<=rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result;
when "100" =>output<=covariance_result;
when "101" =>output<= mse_result;
when others=>null;
end case;
end process;



this warning produced:



WARNING:Xst:737 - Found 32-bit latch for signal <output>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.



why? and how can remove this warning??

because you have not assigned output in all cases.

I think it might be the line
This causes the previous output value to be latched.

TrickyDicky said:

because you have not assigned output in all cases.

Click to expand...

when write this process to covere all case of ir(3 downto 1) the below error occur



process(ir,mean_result,variance_result,st_dev_result,rms_result,covariance_result,mse_result)
begin

case ir(3 downto 1) is
when "000" =>output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result;
when "001" =>output<=variance_result;
when "010" =>output<=st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result;
when "011" =>output<=rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result;
when "100" =>output<=covariance_result;
when "101" =>output<= mse_result;
when "110" =>NULL;
when "111" =>NULL;

end case;
end process;



ERROR:HDLParsers:812 - "G:/project/VHDL/project/again/step1/main.vhd" Line 219. A value is missing in case.

how can overcom this error and the same time covered all case of ir(3 downto 1).

- - - Updated - - -

Rog232 said:

I think it might be the line

Code:

when others=>null;

This causes the previous output value to be latched.

Click to expand...

when write this process to covere all case of ir(3 downto 1) the below error occur



process(ir,mean_result,variance_result,st_dev_result,rms_result,covariance_result,mse_result)
begin

case ir(3 downto 1) is
when "000" =>output<=mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result(16)&mean_result;
when "001" =>output<=variance_result;
when "010" =>output<=st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result(19)&st_dev_result;
when "011" =>output<=rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result(19)&rms_result;
when "100" =>output<=covariance_result;
when "101" =>output<= mse_result;
when "110" =>NULL;
when "111" =>NULL;

end case;
end process;



ERROR:HDLParsers:812 - "G:/project/VHDL/project/again/step1/main.vhd" Line 219. A value is missing in case.



how can overcom this error and the same time covered all case of ir(3 downto 1).

Don't put "null" in your "when others" statement. Assign a value to output in that statement.

r.b.

rberek said:

Don't put "null" in your "when others" statement. Assign a value to output in that statement.

r.b.

Click to expand...

Yes, try that...

- - - Updated - - -

Just to clear that up, you must have the when others=> part or you will get an error. Don't use null in it or you will make a latch.

Rog232 said:

Yes, try that...

- - - Updated - - -

Just to clear that up, you must have the when others=> part or you will get an error. Don't use null in it or you will make a latch.

Click to expand...

i don't have value at output when ir(3 downto 01)=110 and 111
what i do to overcome the error??

sarmad88 said:

i don't have value at output when ir(3 downto 01)=110 and 111
what i do to overcome the error??

Click to expand...

Can you tri-state it? "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"

i don't have value at output when ir(3 downto 01)=110 and 111

Click to expand...

Are saying that ir(3 downto 1 ) will never, ever take on the value 110 and 111 by design? If that is the case, then use a synthesis pragma to declare the case statement "full case", but it is still good design practice to put in a default state (when others) with a default value of output.

If values 110 and 111 are achievable, then YOU might not have a value for output, but the real hardware definitely will. Therefore you have to declare a value for output. If you don't care about output on those states, then put any defined value value down (i.e. not X or Z). In order to avoid latches, you have to explicitly declare the value of every element on the left hand side of every statement for EVERY case. This is not optional.

Can you tri-state it? "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"

Click to expand...

This is only useful if output will actually be an output of the FPGA. And there is more to making an output tristate than just making it all Z. If output is an internal signal, then that is a bad idea. FPGA's don't have internal tristate signals.

r.b.