shuva
Newbie
Hello, I was running the example flat flow design for Tessent scan & ATPG tool. I got an error in the 4th stage (insert_scan) while running the set_system_mode analysis command. It says that at cycle 6, time 250, some pin should be 1, but it is simulated as X. I am attaching the screenshot. How can I solve this error? Thank you.