raymond_luo2003
Member level 1
Dear friend,
Usually the purpose of DLL is providing the multiphase clocks with same frequency as the input clock. And the phase shift of the whole delay line is 2-phi. But if the delay range of DLL delay stage is large, the DLL can lock to 4-phi or 2n-phi (n>2) of delay. This false locking will cause the intermediate phases of the delay line to vary from the desired value.
I am confused how to make a circuit to avoid the above problem. Any reference paper and real circuit are well appreciated!
Thanks and best regards,
Raymond
Usually the purpose of DLL is providing the multiphase clocks with same frequency as the input clock. And the phase shift of the whole delay line is 2-phi. But if the delay range of DLL delay stage is large, the DLL can lock to 4-phi or 2n-phi (n>2) of delay. This false locking will cause the intermediate phases of the delay line to vary from the desired value.
I am confused how to make a circuit to avoid the above problem. Any reference paper and real circuit are well appreciated!
Thanks and best regards,
Raymond