scan chain blocked
scan chain blocking will be present due to
1) uncontrollable clock
2) uncontrollable set/reset signals !!
uncontrollable signals will be present in ur design incase if ur control signals ( clock, set/rst) of the FF, comes from a combinational logic !!!
means to say tht wen u apply the scan vectors, the patterns ( gen by ur ATPG tool) cannot successfully traverse thru all the FF in the scan chain
This problem should hv been fixed at the DFT compiler level itself, evn b4 the generation of ATPG vectors !!!
The reason is tht, while fixing the DRC errors , the DFTC mite not have fixed it completely, its advisable to manually( by specifying the insertion of MUX or and or OR gates .... depends ) fix the DRC error !!!
are there multiple clock in ur design ??? ... if so, LOCK UP latches should also be inserted when there are multiple clock domains in the same scan chain !!
Please chk with the tool settings when u are fixing hte DRC errors, tht should solve the problem !!
WBR
Lakshman