How to simulation the LDO (NMOS type) loop stability?

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tommydidi

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Guys,

I am design a NMOS LDO. Now I have finished the charge pump (switched cap) and working on the err amp. The questions I have for you guys are:

1. Do I need a buffer stage for the err amp?
2. How can I simulate the whole loop stability? Not sure how to model the charge pump, any idea?


Thanks.
 

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