how to simulation switch Cap filter in hspice

[andy2000a]

Hi
switch Cap use clock for get equ_R valuse , and I simulation AC response by this method .. but if clock have gitter .. how to simulation it
in hspice ...

in .tran simulation we can monitor Switch_Cap and get a "resistor value"
but in .AC simulation can not use clock ...

thank you

 

[ynhe]

Hi
A general class of sampled data problems can be formulated using the Z transform theory and simulated using HSPICE.

ynhe

 

[Jet_wu]

There is some example about it in the second version of "CMOS Analog circuit design" written by Allen

 

[kamalakkannan]

can u help

hi andy,
i have designed one POR circuit.comparator has reset threshold of 50mv.
many company's POR datasheet has reset threshold hysterisis around 40mv-60mv.
actually power suplly(VDD) is bound to have around 100mv to 150mv noise even after putting decoupling capacitors at VDD pin in pcb board.which is accetable from the system design point of view.
does it mean that comparator output will keep toggling due to 150mv noise in VDD line because comparator is designed to have hysterisis less than 50mv.
so , POR logic will continously low even when VDD pin higher than threshold trip point level.
do you have answer for this.
plz give me personal id if u can.

best regards,
kamal.