vivsim
Junior Member level 3
i simulated the buck DCDC SSM using spice, PWM using Ridly's model, I compared AC simulation results and Transient results, the two simulation doesn't meet well , i don't know what's wrong, can anyone give me some suggestion ?
i think if change ESR , the loop's phase margin is changed too, but the Transient simulation have not any change
i think if change ESR , the loop's phase margin is changed too, but the Transient simulation have not any change