How to simulate the sensitivity of CML latch

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bageduke

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I always saw some papers that showed the sensitivity curves when they used CML latch as frequency divider. I am wondering how they simulated this kind of curves.

What I can imagine is that they fixed the input frequency, swept input voltage, and then found out what the minimum voltage level to make divider work. After this, they changed to another frequency and repeated above steps until the whole frequency range was simulated.

Am I right, or there is another easier way to do it?

Thanks a lot
 

Yes, you are correct. You also might want to force either a pulse or sine wave at the input and see what the difference in input sensitivity you will get.
 

Thanks, that is my question!
 

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