How to simulate the OP and get the settling time?

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aidenbu

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OP settling time

I am designing the pipeline ADC. For the Sample and Hold circuit, how can I simulate the OP used for it and get the settling time? I only get the Unity Gain Bandwidth and Phase Margin. I am not very sure that if it can keep the settling time enough.
 

OP settling time

Besides bandwidth, Opamp setting time is related to slew rate as well. I suggest you do transcient analysis.
 

Re: OP settling time

Thank you very much!
My op settling time needs 4ns. My unity gain bandwidth is 650Mhz. My load cap is 2.5pf. Output current is 1.2mA. I am not sure if such UGB and output current can satisfy the settling time or not. Can you give me some advises?
 

Re: OP settling time

I only know it is related to small signal analysis,determined from
location of the poles and zeros in the small signal equitment circuit.
i don't know how does the pipeline ADC work.
maybe output current is related the large signal analysis .
hehe
 

Re: OP settling time

OP settling time is related to bandwidth and slew rate.
If your op bandwidth is 650MHz, your op settling time may be 7.5ns to 10.5ns in transcient analysis.
 

Re: OP settling time

For a step response, the settling consists of two phases: the slewing phase and the settling phase.
The slew-rate can depend either on the internal slewing current, or the external load driving capability.
The settling phase depends on both the gain-bandwidth product and the phase margin(kind of inter-related) . Have a phase margin of 50-60 for a good settling. Also, the presence of pole-zero doublets before the unity gain frequency can severely degrade the settling time (not very apparent during ac analysis). So do a transient analysis first, and check if its slow in the slewing or the settling phase. That should narrow down your problem.
 

Re: OP settling time

Thank all of you very much! I am sincerely appreciate your analysis and advises for my problem.
How can I do such a transistant analysis for the OP. How can I check the op's step response? I have read some paper. They show some transistant results about OP's transistant step response and settling time, such as a pulse output of the OP. I don't know which circuit I need to connect OP to and can get the step response and transistant analysis. Can some friends give me some advises?
 

OP settling time

Use cadence or hspice do trans analysis.
 

Re: OP settling time

Assuming the settling erro is ε, then the settling time is

ε=exp(-t/k)

k: the feedback factor•UGB;

So, first you have to determine how many bits every stage is about you pipeline ADC.

And , know the ε .

After this, consider the feedback factor of Sample phase, receive the UGB(S);

And, consider the feedback factor of hole phase, receive the UGB(H);

Then , you can determine the UGB=max(UGB(S), UGB(H)).

Maybe, the Slew-Rate limits the THD, But, when the UGB is increased, the Slew-Rate can be increased in the meanwhile.

Consider what is your main parameter about the SNR or SNDR, you can improve the Slew-rate or UGB.
 

OP settling time

jiangwp, what you have said is very good, are there some materials you can give us?
 

OP settling time

razavi's bk has good description on slew rate and settling time.
 

Re: OP settling time

if it is possible u plz send the specs regarding the speed and resolution of ur sample and hold for Ex. if the speed is 20MSPS and resolution is 4 bit then the min settling time required for the opamp should be less then 12.5ns.
 

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