Perhaps you want to simulate it, the way you would test
it in an ATE environment. That is, wrap an integrator around
the whole thing, making it a negative feedback system.
Then you run the clock as normal, you apply an input
voltage to the "free" terminal and you read the input difference
voltage after you've had enough clocks to settle the integrator
to a stable output.
If you use equal resistor dividers on the input and integrator-
feedback paths this will help you work at lower offsets
in a noisy test environment, and you can take your measurement
off the integrator output before the down-scaling for a more
robust signal.