How to simulate the interference noise in PLL?

[flyinspace]

pll causes interference

Hello,
As we all known, Phase Noise of PLL can be simulated in SpectreRF by PSS & Pnoise analysis. However, the result of PN just includes the nature noise of transistors and resistors. My problems are:
1, The supply power and the bulk also induce the noise into PLL circuit, then how to consider their effects to the entire PN result?
2, Now PLL circuit is generally in the mixed signal IC or SOC, then the interference noise from digital parts can also contribute to the PN though it's effect can be reduced by reasonable layout. How can we consider this effect?
3, Can these effects be simulated by SpectreRF? If it can, then how to do it?

 

[uncle_urfi]

pll interference

For substrate noise, you have to model the substrate first.
There are some Kluwer books on injection of noise thru substrates.

Empirically, the results of the PSS simulation are about 10dB better than the actual measurements unless you have done something too carelessly with the layout.

This can be minimized by using inductors between VDD and the pmos bias transistors, esp. in the ring oscillators. and connecting grounds of the analog and digital circuits on-chip.(yes, that 's right you read it correctly, have to connect the grounds onchip)

Look at the attached thesis of Li Lin from Berkeley. She has used 200mV signal at different frequencies in series with thepower supply to measure the interference.