giggs11
Member level 3
Hi all,
I completed a design of 40,000 transistors through P&R and it contains a total of 26 input bits.
I've simulated the design by doing a transient analysis for 1.9us and by specifying their transitions for every 25ns for each input bit using the piecewise linear command.
I also wanted to print out the current flowing through the Vdd sources to size the power rails accordingly. For that I used the command below:
.print tran i(vvdd1) i(vvdd2)
.power vvdd -----> power measurement
The problem is the results. Get ready for this... The power consumption was near 2kW and the current went up as high as 800A...thats right Ampere. Is this logical or is there something wrong with my simulation commands.
All my transistor have a W/L ratio of 14 with W=7u and l=0.5um and i'm using the AMI 0.5um process technology.
My question is simple...are these numbers practical and please can someone comment on my simulation technique.
Confused for an amateur,
Giggs.
I completed a design of 40,000 transistors through P&R and it contains a total of 26 input bits.
I've simulated the design by doing a transient analysis for 1.9us and by specifying their transitions for every 25ns for each input bit using the piecewise linear command.
I also wanted to print out the current flowing through the Vdd sources to size the power rails accordingly. For that I used the command below:
.print tran i(vvdd1) i(vvdd2)
.power vvdd -----> power measurement
The problem is the results. Get ready for this... The power consumption was near 2kW and the current went up as high as 800A...thats right Ampere. Is this logical or is there something wrong with my simulation commands.
All my transistor have a W/L ratio of 14 with W=7u and l=0.5um and i'm using the AMI 0.5um process technology.
My question is simple...are these numbers practical and please can someone comment on my simulation technique.
Confused for an amateur,
Giggs.