How to Simulate in Questasim

jayanth.devarayanadurga · Jul 21, 2013

This is the first Verilog code I wrote. It compiled successfully in Questasim 10.1b. I want to know how to Use the simulator to simulate the project.

Code Verilog - [expand]
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// 2-input OR gate
 
 
`timescale 1ns / 1ps
 
module OR2gate(A, B, F);
 
   input A;
   input B;
   output F;
   reg F;
 
   always @ (A or B)
   begin
   
      F <= A | B;
   end
 
endmodule

TrickyDicky · Jul 21, 2013

first, you will need a testbench to stimulate the inputs.

jayanth.devarayanadurga · Jul 21, 2013

Explain the steps. I need to see the wave form for my OR gate.

mrflibble · Jul 21, 2013

step 1: read a tutorial/book/whatever about writing testbenches
step 2: write testbench
step 3 (optional): rtfm of your simulator (questasim in this case)
step 4: run testbench
step 5: profit!

For example see this: https://www.asic-world.com/verilog/art_testbench_writing.html

How to Simulate in Questasim

jayanth.devarayanadurga

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TrickyDicky

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jayanth.devarayanadurga

jayanth.devarayanadurga

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mrflibble

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Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19	// 2-input OR gate `timescale 1ns / 1ps module OR2gate(A, B, F); input A; input B; output F; reg F; always @ (A or B) begin F <= A \| B; end endmodule

How to Simulate in Questasim

jayanth.devarayanadurga

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TrickyDicky

Advanced Member level 7

jayanth.devarayanadurga

Banned

mrflibble

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