I'm now designing a SH circuit of a 8bit pipelined ADC. I know the capacitor mismatch is a very important consideration of a ADC. But I don't know how to simulate the capacitor mismatch. should I use monte carlo? and how ?
The simulation can not get the capacitor mismatch value. You can do a post layout extraction. From the extraction netlist, you can find the mismatch value.
To bigpop, cap mismatch doesn't source from layout even if post layout extraction obtains different parasitic capacitance for two caps.
Added after 21 minutes:
Generally, cap mismatch doesn't affect SH circuit much, but not multiplying DAC in pipeline ADC design. Some modeling can used to evaluate cap mismatch.
Re: how to simulate capacitor mismatch of a pipeline SH circ
if this mismatch comes from process variation, post layout simulation can not give you help on this mismatch effect. I always calculate manully. you could get a mismatch report from foundry and use sigma data to calculate
If it is modelled monte-carlo has an mismatch option next to the corner option. Otherwise hand calculate your worst case capacitors and simulate with those values. Preferably you should do both to get a sanity check on both methods.
Re: how to simulate capacitor mismatch of a pipeline SH circ
I have used the following two ways
1.a. obtain mismatch data from foundry or by looking at your models for capacitors of that size.
1.b model the switch cap section in matlab and run full montecarlo to see affect of mismatch
1.c use information to evaluate if smaller/larger sizes need to be used.
2.a run montecarlo in simulator environment
2.b braid hair while waiting for sims to finish
2.c write that great [insert country here] novel you've always been wanting to write
2.d teach self foreign language
2.e examine finished sim results respond similarly as 1.c