How to simulate a CML Latch or Mux in Cadence

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antaryami.mt.er09

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Hi....
I having a tough problem in simulating the CML circuit, though it is similar to diff amp i don't have idea how to
put a logic 1 or logic 0 for a particular swing such that my CML circuit can drive the next stage easily.

I mean .... how to put the pulse source during transient simulation ; over certain common mode voltage ?? and what
would be the pulse voltage levels ? and how to decide ?
Kindly help............
 

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