Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to simulate a CML Latch or Mux in Cadence

Status
Not open for further replies.
A

antaryami.mt.er09

Member level 2
Member level 2
Joined
Aug 14, 2010
Messages
49
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
INDIA
Activity points
1,576
Hi....
I having a tough problem in simulating the CML circuit, though it is similar to diff amp i don't have idea how to
put a logic 1 or logic 0 for a particular swing such that my CML circuit can drive the next stage easily.

I mean .... how to put the pulse source during transient simulation ; over certain common mode voltage ?? and what
would be the pulse voltage levels ? and how to decide ?
Kindly help............
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top