How to simlulation the stability of a LDO?

[jiangwp]

The key parameter of LDO is the stablility.
But how do we simulaltion of a LDO?
which loop is selected for stability of LDO with close loop or open loop?
if the open loop is selected, where is the open point?

 

[Vamsi Mocherla]

You have to cut the loop at the input terminal which sees the feedback. You have to do Loop test where the loop is cut - not open loop or closed loop. On your load you have to put a cap and a res and see the variations of Phase Margin when you sweep them

 

[lastdance]

The easiest way to test a LDO's stability is to step the load, up and down.
Observe the waveform, and adjust compensation until you see a damped waveform. AC sometime give you good PM, but you may be umdamped or have peakings. But you must always do a sanity check in AC, to determine the location of poles and zeros.
you must also do hand calculations to see if it matches the simulator, otherwise, you need to account for it. u cannot ignore what the simulator is telling you until u prove that it is wrong.

 

[rongli]

I can't make a circuit into a symble.when I want a high gain erramp, I can't realise it.

 

[Vamsi Mocherla]

In cadence, you can select the circuit, and then extract the symbol from schematic.

Go to Design ------> Create Cellview -------> From Cell view.

Then you will get a form to create the symbol. You can edit the placing of pins in that.

 

[mady79]

Do not forget to put the ESR with the cap while doing simulations .

 

[mady79]

Best way to measure stability to put a step load at the output and do a tran analysis & see output waveform for stability .Try to tweak ESR a little .

 

[mark_nctu]

use ESR to reduc first pole to enhance LDO's bandwidth.

 

[ambreesh]

Dear mark_nctu,
The first pole u have mentioned is it the dominant pole u mean.
If u reduce the ESR u also move the LHS zero away. Which is used to take care of the non-dominat pole.

 

[kanbin　]

You can simlulation open loop like OP amplifier.

 

[sergeyr77]

1. AC check of phase margin, no matter closed loop simulation or open:
plots Vfb/(Vin-Vfb) both for phase and magnitude. Criterion PM > 70
2. Trans. Steps at the input (line regulation) and disterbance at the output (load regulation). No overshoots are allowed