How to set the bias voltage of cascode op?

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hi all,
I am designing a cascode op. It really works when I use the way of try and error
to set bias voltages in the op. But I don't know if there is ease way?
thanks
jason
 

assume the bias voltage is vb.,
the below transistor vds is vgs1-vth1.
so the vb should be grater than vgs1-vth1+vgs2.
it will give the minimum value of vb for the cascode opamp.
 
hi nagula,
my op is two stage with second stage cascoded. you know it like improved basic two stage OP. I just add one common gate PMOS between output and former PMOS current source. The same way add one NMOS between output and second amplifier NMOS transistor. My problem is such configuration is not robust. if gate voltage of amplifier NMOS changed a little, some transistor will
get into linear region. would you like help me ?
Thanks
 

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