how to set the bandwidth of pll ?

[xihuwang]

Hi :
To decrease the switch noise, the bandwidth must be set less than
1/20 of reference clock .
I want to know , for a PLL for clock generate with ref clk frequeny of 8M and output frequency 8*16M , is it okey to set unit bandwidth (8/20)M or more less ?

 

[saro_k_82]

This is just the upper limit for the BW (I would use 1/10 rather)., but the BW is set either by phase noise optimization or lock time optimization.
BW for phase noise optimization is set at the frequency where the contribution from the VCO balances the contribution from the PFD-CP, dividers and the reference.