how to set global include in synplify, like vivado "set global include"

skyworld_cy · Dec 21, 2023

Hi,
I have used `define in several verilog files like

Code:

`ifdef FPGA
   ......
`else // FPGA
  ....
`endif // FPGA

I use an .inc file to enable/disable these defines macros. In vivado I can set this inc file as "set global include" so that every verilog file see these define macros. Is there is a way I can implement the same function in synplify? thanks.

regards
skyworld

FvM · Dec 21, 2023

How about using an actual 'include statement?

skyworld_cy · Dec 21, 2023

FvM said:
How about using an actual 'include statement?

there are too many files used those defines. I don't want to add "include" for every verilog file.

FvM · Dec 21, 2023

skyworld_cy said:
there are too many files used those defines. I don't want to add "include" for every verilog file.

But that's the Verilog way to do it.

skyworld_cy · Dec 21, 2023

FvM said:
But that's the Verilog way to do it.

with vivado, I can set this inc file as "global include". In this way every verilog file could know what is defined in inc file. I'm not sure how to do this in synplify

FvM · Dec 21, 2023

"Global include" is a non-standard Verilog extension in Vivado, not provided by other tools (at least I'm not aware of). If you want portable code, use standard Verilog language means.

how to set global include in synplify, like vivado "set global include"

skyworld_cy

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how to set global include in synplify, like vivado "set global include"

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